SoC Transaction Reordering for Memory Consistency and Identifier Saturation
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Solution Overview
Problem
Current signal processing systems, such as System-on-Chip (SoC) systems, face challenges in ensuring memory consistency and performance due to constraints imposed by protocols like AMBA AXI, particularly when handling multiple memory transactions and address remapping, leading to inefficiencies and saturation issues with transaction identifiers.
Innovation Solution
A reordering arrangement that assigns consistent identifiers to transactions based on target modules and system conditions, using a bit-compression system to avoid identifier saturation, ensuring compliance with memory-consistency protocols like AXI while maintaining high performance in multi-DDR systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware techniques are used to balance memory loads among multiple memories, then memory load balancing is improved, but hardware complexity increases
Solution Approach 1:
The patent introduces a reordering unit as an intermediary component between the processor core and the memory system. This reordering unit handles the complex task of tracking and managing transaction identifiers and target module mappings, effectively mediating between the simple processor core and the complex multi-memory system. The reordering unit absorbs the hardware complexity while presenting a simplified interface to the processor, thus improving memory load balancing without requiring the processor core itself to become more complex.
2Adaptability or versatility
If transaction identifiers are assigned via network for memory access, then memory access flexibility is improved, but identifier saturation occurs
Solution Approach 1:
The patent dynamically changes the parameters of transaction identifiers by tracking their usage status and target module assignments. When an identifier becomes available (its transaction completes), the system reuses it for new transactions. The reordering unit maintains mapping information that allows flexible reassignment of identifiers to different target modules over time, thus improving memory access flexibility while preventing identifier saturation through efficient reuse.
Solution Approach 2:
The patent implements a mechanism where completed transaction identifiers are discarded from active use and recovered for reuse in new transactions. The reordering unit tracks which identifiers are currently in use and which are available, enabling the system to recover and reuse identifier values rather than continuously allocating new ones. This prevents identifier saturation while maintaining the flexibility needed for dynamic memory access patterns.
3Reliability
If protocol ordering constraints are enforced for memory transactions, then memory consistency is improved, but system performance deteriorates
Solution Approach 1:
The patent segments the memory transaction handling into two independent parts: ordering enforcement and target module mapping. The reordering unit separately manages the ordering constraints (tracking identifier usage and completion status) from the actual memory access operations. This segmentation allows the system to enforce protocol ordering requirements without forcing sequential execution of all memory transactions, as multiple identifiers can be tracked and reused in parallel, thus maintaining memory consistency while preserving system performance.
Data Source
AI summary
In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.