Post-Silicon Validation Test Generation via Scenario Reuse
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Solution Overview
Problem
Current post-silicon validation processes require significant effort and time to construct new tests from scratch, whereas existing simulation and emulation scenarios are not efficiently utilized to generate post-silicon validation tests that effectively challenge system on chip (SOC) components.
Innovation Solution
A method and system that select and combine validated scenarios originally designed for simulation tests, allowing for parallel execution and looped scenarios to generate post-silicon validation tests, with the option to amend actions in each loop, ensuring scenarios do not exceed resource limitations, thereby generating efficient and diverse tests with minimal user effort.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If new post-silicon validation tests are constructed from scratch, then test effectiveness and coverage can be optimized, but significant effort and time are required
Solution Approach 1:
The system performs preliminary actions by pre-validating simulation scenarios during the simulation phase. These pre-validated scenarios are then reused in post-silicon validation, eliminating the need to create and validate tests from scratch at each stage. The scenario validation is done in advance, and the same scenarios are leveraged across different validation phases.
Solution Approach 2:
The system creates copies of validated simulation scenarios and reuses them for post-silicon validation. Instead of creating new tests, the system copies existing validated scenarios and adapts them for use in post-silicon validation environments, significantly reducing construction time while maintaining test quality.
2Loss of time
If simulation scenarios are reused for post-silicon validation, then test construction time is reduced, but the scenarios may not effectively challenge SOC components at runtime
Solution Approach 1:
The system dynamically adapts simulation scenarios for post-silicon validation by modifying their execution context. Scenarios are transformed from static simulation models to dynamic runtime executions on actual SOC hardware, allowing them to effectively challenge components in the target environment while retaining their original validation logic.
Solution Approach 2:
The system changes key parameters when reusing scenarios across different validation stages. Simulation scenarios are transformed by adjusting execution parameters, timing constraints, and hardware interaction modes to match post-silicon validation requirements, ensuring scenarios remain effective while reducing reconstruction time.
3Reliability
If multiple scenarios are executed in parallel, then validation coverage is improved, but resource limitations may be exceeded
Solution Approach 1:
The system implements feedback mechanisms to monitor resource utilization during parallel scenario execution. When resource limitations are detected, the system provides feedback to adjust scenario execution, such as serializing conflicting scenarios or allocating resources dynamically, thereby maintaining validation coverage within hardware constraints.
Solution Approach 2:
The system segments scenarios that conflict for resource usage and executes them in separate time slots or threads. By dividing the validation workload into manageable segments that don't exceed resource limits, the system achieves comprehensive coverage while respecting hardware constraints through structured scenario organization.
Data Source
AI summary
A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.