SoC Verification Platform Bypassing CPU Boot via Bus Function Model
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Solution Overview
Problem
Current verification methods for System on Chip (SoC) technology are time-consuming and require deep CPU knowledge, with CPU booting processes delaying verification progress and limited reuse of software test programs.
Innovation Solution
A verification platform and method that includes a central processing unit, bus function model unit, and Universal Verification Methodology test instance, allowing flexible simulation through selection switches for connecting components and interfaces, enabling efficient testing via multiple paths (UVM, DPI, and CPU paths) to shorten verification cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If CPU booting process is performed before test execution, then CPU can execute software code, but verification time is extended due to mandatory booting process
Solution Approach 1:
The verification platform segments the testing approach into two independent paths: UVM test instances that test bus interface directly without CPU booting, and software test instances that compile and execute through CPU. This segmentation allows bypassing the CPU booting process for UVM tests, reducing verification time while maintaining CPU execution capability for software tests.
Solution Approach 2:
The bus function model unit acts as an intermediary between the UVM test instances and the bus, enabling direct testing of bus interface functionality without requiring CPU involvement. This intermediary mechanism allows verification engineers to test bus protocols and interfaces independently, eliminating the time-consuming CPU booting process for interface verification.
2Adaptability or versatility
If CPU-based verification method is used, then software code execution is enabled, but deep CPU knowledge including assembly language is required
Solution Approach 1:
The verification platform provides universal testing capability through UVM test instances that can verify bus interface functionality without requiring CPU-specific knowledge. The platform supports both UVM-based universal interface testing and CPU-based software testing, making it adaptable to different verification needs while reducing the complexity barrier for interface verification.
Solution Approach 2:
The bus function model unit creates a simplified model/representation of the bus interface that can be tested independently through UVM test instances. This copying approach allows verification of bus functionality without needing to understand the complex CPU internal workings, reducing the knowledge requirement while maintaining verification capability.
3Loss of time
If UVM test instances are used, then bus interface testing is enabled, but software test program reuse is limited
Solution Approach 1:
The verification platform merges UVM test instances and software test instances into a unified testing framework that can selectively execute different test types. This merging allows the system to combine the fast interface verification capability of UVM with the reusability of software test programs, enabling comprehensive verification while maximizing test program reuse across different verification scenarios.
Data Source
AI summary
The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.