SoC Verification Platform Using Dynamic Bus Function Model
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Solution Overview
Problem
Current verification methods for System on Chip (SoC) technology are limited by the need for fixed configuration and stimulus, leading to time-consuming direct tests with poor test coverage, and lack of dynamic control over the verification platform, which hinders efficient simulation progress.
Innovation Solution
A verification platform and method that utilizes a bus function model unit with a storage area, allowing a Universal Verification Methodology test instance to generate and store constrained random parameters and controls, enabling dynamic configuration and execution status monitoring to improve test coverage and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If direct tests with fixed configuration and stimulus are used, then the verification process is simple to implement, but the test coverage is insufficient and requires building a large number of tests which is time-consuming
Solution Approach 1:
The patent transforms the static, fixed configuration of direct tests into a dynamic system where a software program running on the CPU can randomly generate and adjust test configurations and stimuli during execution. This allows the verification platform to adaptively explore different test scenarios without manually building numerous fixed tests, thereby improving test coverage while reducing the time required to create test cases.
Solution Approach 2:
The patent enables randomization of test parameters (configuration and stimulus) through software control. Instead of using fixed parameter values in direct tests, the system randomly varies parameters during test execution, allowing comprehensive coverage of different test scenarios with a single flexible test framework rather than requiring multiple pre-built fixed tests.
2Adaptability or versatility
If software program is used to control verification platform, then dynamic control is achieved, but the software program cannot dynamically control the verification platform without recompilation each time configuration changes
Solution Approach 1:
The patent pre-establishes a storage area in the bus function model unit before test execution. This storage area is specifically designed to hold test parameters and execution status information, allowing the software program to dynamically read and write data during test execution without requiring recompilation. The preliminary setup of this data storage infrastructure enables flexible dynamic control while maintaining high simulation efficiency.
Solution Approach 2:
The patent introduces a bus function model unit with a storage area as an intermediary between the CPU-running software program and the verification platform. This intermediary structure allows the software to dynamically control test configurations by reading and writing to the storage area through the bus, without requiring direct recompilation or modification of the software code when configurations change, thus achieving both adaptability and efficiency.
3Ease of operation
If CPU runs software program for verification, then flexible test configuration is possible, but the verification process lacks direct access to execution status information for real-time monitoring
Solution Approach 1:
The patent merges the storage of test parameters and execution status information into a single unified storage area within the bus function model unit. This combined storage structure allows both the test configuration data (written by the UVM test instance) and execution status information (written by the software test instance) to coexist and be easily accessed by respective components, eliminating information loss while maintaining configuration flexibility.
Solution Approach 2:
The patent establishes a feedback mechanism where the software test instance writes execution status information to the storage area, which is then readable by the UVM test instance. This feedback loop enables real-time monitoring of test execution status, allowing the verification system to track and analyze test progress and outcomes dynamically without compromising the flexibility of test configuration through software control.
Data Source
AI summary
The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.