SoC Verification Platform Selective Component Simulation
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Solution Overview
Problem
The conventional System on Chip (SoC) verification methods face challenges in verification completeness and efficiency due to the need to simulate all components, leading to high resource consumption and long verification times, especially when verifying a single processor.
Innovation Solution
An improved method for SoC verification is introduced, which includes establishing a component library, creating a control file with parameters, and generating a verification platform by selecting required components and excitations from libraries, allowing only the necessary components to participate in simulation, thereby reducing resource consumption and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all components are simulated in the verification structure, then verification completeness is improved, but verification resource consumption increases and verification time extends
Solution Approach 1:
The verification structure is segmented into multiple independent verification environments, each corresponding to a specific processor or component. This allows selective activation of only the required verification environment for the current verification task, rather than simulating all components simultaneously. The segmentation enables independent configuration and execution of verification cases for individual processors while maintaining overall system verification completeness.
Solution Approach 2:
The patent implements partial action by allowing the verification system to activate only the necessary portion of the verification structure for each verification task. When verifying a specific processor, only that processor's verification environment is activated, while other processors and components remain inactive. This partial activation significantly reduces resource consumption and verification time while maintaining verification effectiveness for the target component.
2Reliability
If a complete verification environment is built, then verification coverage is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent creates a universal verification platform that can serve multiple processors and components through a single integrated structure. This verification platform is designed with multi-functionality, allowing it to be configured for different verification scenarios by activating specific verification environments. The universal structure eliminates the need to build separate verification environments for each processor, reducing overall device complexity while maintaining comprehensive verification coverage.
Solution Approach 2:
The verification structure implements dynamic configuration capabilities, allowing the system to adaptively activate or deactivate verification environments based on the current verification requirements. This dynamic nature enables the verification platform to transform its structure and resource allocation according to different verification tasks, reducing complexity for specific tasks while maintaining the capability for comprehensive system verification when needed.
3Reliability
If all processors and co-processors are simulated, then system-level verification completeness is improved, but verification time and resource consumption increase
Solution Approach 1:
The system-level verification is segmented into multiple independent verification tasks, each focusing on specific processors or components. This segmentation allows the verification system to execute only the relevant verification tasks for the current development stage or bug investigation, rather than running all possible verification scenarios. The segmented approach maintains system-level verification completeness over time while significantly reducing the time required for individual verification iterations.
Solution Approach 2:
The patent implements preliminary action by pre-configuring multiple verification environments in advance, each optimized for specific processors or components. These pre-configured environments include necessary test cases, stimuli, and expected results. When verification is needed, the system can quickly activate the appropriate pre-configured environment without requiring time-consuming setup, thus reducing verification time while maintaining comprehensive system-level coverage through the collection of all pre-configured environments.
Data Source
AI summary
A method for system-on-chip (SoC) verification is disclosed. The method includes: establishing a component library including at least an interface protocol component, a bus protocol component and a verification component for the SoC; creating a control file according to a verification requirement; establishing a software library for each processor of the SoC to run according to the verification requirement, and establishing an excitation library for corresponding components in the component library; establishing a script library including multiple script files based on the verification requirement and the control file; parsing, by the script, the control file of the verification platform to obtain control parameters of the verification platform when a verification scenario is determined; selecting a required component from the component library and selecting a required excitation from the excitation library to generate the verification platform according to the control parameters; and verifying the SoC by the verification platform.