SoC Verification Metadata Flow for Automated UVM Test Generation

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Solution Overview

Problem

Existing systems-on-chip (SoC) verification methods are inefficient and labor-intensive, particularly in generating complex test scenarios for verifying multiple intellectual property cores, leading to increased resource requirements and reliance on skilled engineers.

Innovation Solution

A system and method for automatically generating universal verification methodology (UVM) test code by combining sequence codes and task codes stored in a library, forming metadata, and converting it into UVM test code using an interpreter, thereby simplifying the creation of complex test scenarios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual methods are used to generate test scenarios for SoC verification, then verification can be performed, but the process becomes labor-intensive and requires skilled engineers

Engineering Contradiction:

Improveverification reliabilityVSAvoidease of generating test scenarios

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The system enables self-service automated generation of test scenarios by combining sequence codes and task codes through metadata processing, eliminating the need for manual intervention by skilled engineers while maintaining verification reliability

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

Metadata serves as an intermediary element that bridges sequence codes and task codes, enabling automated combination and generation of test scenarios without requiring direct manual coding expertise

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If complex test scenarios are generated manually to increase verification reliability, then verification quality improves, but resource consumption increases

Engineering Contradiction:

Improveverification reliabilityVSAvoidresource consumption

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The system uses templates and predefined code structures that can be reused and copied multiple times to generate complex test scenarios automatically, reducing the need to create each scenario from scratch and thereby reducing resource consumption while maintaining verification reliability

Inventive Principle:

Principle #26Copying

3Productivity

If automated generation of test scenarios is implemented, then productivity improves, but the complexity of the generation system increases

Engineering Contradiction:

Improvetest scenario generation efficiencyVSAvoidcomplexity of code generation system

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The code generation system is segmented into distinct functional modules: sequence code storage, task code storage, metadata processing, and code generation. This modular architecture improves productivity while managing system complexity through clear separation of concerns

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12524322B2System, method, and computer-readable storage medium for system-on-chip verification

Publication Date: 2026.01.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A system for verifying a system-on-chip (SoC) including a plurality of intellectual property cores (IPs) includes a library configured to store a plurality of sequence codes corresponding to the plurality of IPs and a plurality of task codes for driving the SoC, and processing circuitry configured to, generate at least one test scenario by combining one or more of the sequence codes and one or more of the task codes stored in the library, generate metadata based on the at least one test scenario, the metadata having a specific format, and generate universal verification methodology (UVM) test code based on the metadata.