SoC Header Switch Voltage Control for Stable Clock Gating
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Solution Overview
Problem
Existing system on chip (SoC) technologies face challenges in maintaining stability of internal power sources, leading to unstable power states in electronic devices, which can result in inefficiencies and increased power consumption.
Innovation Solution
The implementation of a system on chip (SoC) that includes a power manager with header switch circuits and a voltage regulator to monitor and adjust supply voltages, ensuring a minimum supply voltage is maintained for cores in a clock gating state, thereby stabilizing the power state and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage is reduced to save power, then power consumption is reduced, but the clock gating state cannot be maintained
Solution Approach 1:
The voltage regulator dynamically adjusts the supply voltage parameter to different levels based on the operational state of the core. When the core is in clock gating state, the regulator maintains a minimum threshold voltage to preserve the state, while allowing voltage reduction during normal operation to save power, thus resolving the contradiction between power saving and state stability
Solution Approach 2:
The system implements feedback control where the voltage regulator continuously monitors the supply voltage and core state, and adjusts the voltage accordingly. When the core enters clock gating state, the feedback mechanism detects this change and automatically raises the voltage to the minimum required level to maintain the state, preventing power-induced state loss
2Reliability
If the supply voltage is maintained at a high level, then the clock gating state is stable, but power consumption increases
Solution Approach 1:
The voltage regulation system transitions from a static high-voltage approach to a dynamic voltage adjustment mechanism. The voltage is adaptively changed based on real-time operational conditions: high voltage is applied only when necessary to maintain clock gating state, while lower voltage is applied during normal operation, optimizing the balance between stability and power consumption
Solution Approach 2:
Instead of continuously applying high voltage to ensure stability, the system applies voltage precisely at the minimum necessary level and only during the specific condition (clock gating state) when stability is critical. This partial action approach avoids the excessive power consumption of continuous high-voltage maintenance
3Use of energy by moving object
If voltage regulation is implemented, then power consumption is optimized, but device complexity increases
Solution Approach 1:
The voltage regulator is designed to serve multiple functions: it provides general voltage regulation for power optimization, detects core operational states, controls header switch circuits, and maintains minimum voltage thresholds. By consolidating these functions into a single multi-functional module, the patent reduces overall device complexity while achieving power consumption optimization
Data Source
AI summary
A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.