SoC Voltage Droop Detection Circuit Clock Modulation
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Solution Overview
Problem
High-performance semiconductor circuits in system-on-chip (SoC) face inefficiencies due to increased power consumption from setting high guard bands to prevent voltage droops, which can lead to decreased product efficiency.
Innovation Solution
A system-on-chip with a voltage droop detection circuit that monitors supply voltage and adjusts the frequency of an adaptive clock signal to manage voltage droops, reducing power consumption by modulating the clock signal when a droop is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high guard band is set on the supply voltage to prevent voltage droop, then the reliability of the functional circuit is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable based on real-time voltage conditions. The frequency of the clock signal provided to the functional circuit is dynamically changed according to the detected voltage droop level, allowing the system to adapt to varying voltage conditions rather than maintaining a fixed high guard band setting.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal in response to voltage droop detection. When voltage droop is detected, the frequency of the clock signal is adjusted, which in turn affects the operating characteristics of the functional circuit and allows reliable operation under varying voltage conditions without requiring a consistently high guard band.
2Use of energy by moving object
If the frequency of the clock signal is reduced during voltage droop, then the power consumption is decreased, but the processing speed of the functional circuit is reduced
Solution Approach 1:
The system dynamically adjusts the clock signal frequency based on real-time voltage monitoring. When voltage droop is detected, the frequency is reduced to lower power consumption, and when voltage is stable, the frequency can be increased to maintain high processing speed, creating a dynamic balance between power efficiency and performance.
Solution Approach 2:
The patent implements feedback by monitoring the supply voltage and using this information to adjust the clock signal frequency. The detection circuit continuously monitors voltage levels and provides feedback to the clock generation circuit, which adjusts the frequency accordingly, creating a closed-loop control system that balances power consumption and processing speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient power consumption management by reducing the frequency of the clock signal during voltage droops, stabilizing operations and minimizing the need for a high guard band, thereby decreasing overall power consumption and maintaining system stability.
Implementation Method 1
a detection signal generator configured to generate the detection signal by comparing the reference voltage with the supply voltage to generate the detection signal
Data Source
AI summary
A system-on-chip includes a functional circuit, a voltage droop detection circuit, a clock generation circuit, and a clock modulation. The voltage droop detection circuit includes a voltage droop detection controller, a reference voltage generator, and a detection signal generator.