SoC Voltage Control Loop With Analog Feedback for Low-Latency DCVS
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Solution Overview
Problem
Existing systems incur substantial latency in issuing dynamic VOP requests from sub-systems of a system-on-chip (SoC) to a power management integrated circuit (PMIC), prohibiting load profile aware driving of optimal operating voltages (VOP) due to serialized path latencies and increasing number of rails, leading to missed optimal VOP windows.
Innovation Solution
A control loop system that utilizes a voltage regulator feedback path to dynamically adjust output voltage through a current sink/source drive controlled by the SoC, eliminating dependency on digital resources and interfaces, with a single pin addition on the SoC for die-level voltage feedback sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dynamic VOP requests are issued through existing digital interfaces to PMIC, then voltage regulation is achieved, but substantial latency occurs due to serialized path and increasing number of rails
Solution Approach 1:
The patent extracts the voltage control function from the digital PMIC interface path and implements it directly at the die level within the SoC. By taking out the voltage regulation control from the external PMIC communication path and placing it internally, the serialized digital interface latency is eliminated, achieving direct analog control of the voltage regulator output without going through digital serialization delays
Solution Approach 2:
The patent introduces a new analog feedback path as an intermediary between the SoC and voltage regulator output. This analog path uses a feedback resistor network and comparator to directly sense and control the voltage regulator output, bypassing the digital PMIC interface entirely. The analog intermediary enables direct voltage control without digital conversion delays
2Measurement precision
If additional PMIC pins are added for die-level voltage feedback sensing, then voltage control precision is improved, but device complexity and pin count increase
Solution Approach 1:
The patent makes existing PMIC pins multi-functional by having them serve both as digital control interfaces and as analog feedback sensing points. The same physical pins that carry digital VOP requests are also used to carry the analog voltage feedback signal, eliminating the need for dedicated additional pins while maintaining precise voltage sensing capability
Solution Approach 2:
The patent merges the digital control function and analog feedback sensing function into a single integrated path. By combining the voltage request signal path and voltage feedback sensing path into the same physical interface, the patent achieves precise voltage control without increasing pin count, as both functions share the same hardware resources
Data Source
AI summary
A method for control loop sub-system voltage management is described. The method includes detecting a requested dynamic clock voltage scaling (DCVS) operating voltage in a predetermined voltage range. The method also includes setting a current sink/source drive of a system-on-chip (SoC) according to the requested DCVS operating voltage. The method further includes adjusting an output voltage of a voltage regulator through a voltage regulator feedback path between the voltage regulator and the current sink/source drive of the SoC.