SoC Voltage Offset Control for Board-Specific Power Margins
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Solution Overview
Problem
The manufacturing yield of electronic devices is hindered by the mismatch between the specified and actual supply voltage margins due to board IR drops and PMIC variations, leading to inefficient power management and potential defects.
Innovation Solution
An electronic device determines the actual voltage applied and its characteristics based on board characteristics, allowing for the application of a suitable voltage to the chip, thereby reducing power consumption and preventing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a default voltage is applied to the chip based on ASV group specification, then manufacturing yield is improved by ensuring minimum operating speed, but power consumption increases and voltage margin becomes inefficient due to board IR drop and PMIC variation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the supply voltage to the chip based on measured operating characteristics. Instead of using a fixed default voltage from ASV group specification, the system measures actual operating speed and power consumption, then modifies the voltage parameter to optimize both power efficiency and performance. This allows the voltage to be tuned precisely for each chip-board combination, resolving the contradiction between ensuring minimum speed (reliability) and minimizing power consumption.
2Reliability
If a margin voltage is applied to account for board IR drop and PMIC variation, then operating reliability is improved, but voltage margin becomes excessively large which inhibits efficient power management
Solution Approach 1:
The patent implements feedback by measuring the actual operating speed and power consumption of the chip after mounting, then using this information to determine the appropriate voltage margin. The system continuously monitors performance and adjusts the voltage accordingly, rather than applying a fixed conservative margin. This feedback mechanism allows the voltage to be optimized for each specific chip-board combination, ensuring sufficient margin for reliability while eliminating excessive voltage headroom that would waste power.
3Productivity
If voltage measurement and adjustment circuitry is added to the chip, then power management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by enabling the chip to autonomously measure its own operating characteristics and determine the optimal voltage setting. The chip includes measurement circuitry that monitors its own power consumption and operating speed, then automatically adjusts its voltage without requiring complex external control systems. This self-measuring and self-adjusting capability improves power management efficiency while minimizing the addition of complexity, as the chip serves its own voltage optimization needs.
Data Source
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AI summary
An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.