SoC Wake Logic Gating to Reduce Active-State Power
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Solution Overview
Problem
Existing system designs consume power continuously due to always-on wake logic, irrespective of the system being in an active or low power state, leading to inefficient power management and reduced battery life.
Innovation Solution
Implementing sensors to detect user presence or absence, and controlling wake logic and circuitry for IP blocks in SoC and platform levels, turning off wake logic in active states and selectively turning it on in low power states based on user presence, and defining new power management modes in ACPI specifications to transition devices to D3 state without idle timeouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wake logic is always kept ON to ensure system responsiveness, then system reliability is improved, but power consumption increases continuously
Solution Approach 1:
The patent implements dynamic power management by transitioning wake logic between different power states (D0, D3hot, D3cold) based on system conditions and user presence detection. The wake logic adapts its operational state rather than remaining static, allowing it to be fully operational when needed and powered down when unnecessary, thus resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The system uses sensors to automatically detect user presence and autonomously control the power state of wake logic without requiring manual intervention. The OSPM (Operating System Power Manager) monitors sensor data and automatically transitions wake logic to appropriate power states, enabling the system to serve itself in power management decisions and eliminating continuous power consumption while maintaining responsiveness.
2Use of energy by moving object
If wake logic is turned off in active state to save power, then power consumption is reduced, but system responsiveness deteriorates
Solution Approach 1:
The system performs preliminary actions by detecting user presence before transitioning wake logic to low-power states. Sensors monitor for user presence in advance, and the OSPM uses this information to proactively maintain wake logic in operational states when users are present, preventing responsiveness issues before they occur. This preliminary detection and preparation resolves the contradiction by ensuring wake logic is ready when needed while saving power when appropriate.
3Productivity
If sensors are added to detect user presence for power management, then power management efficiency is improved, but device complexity increases
Solution Approach 1:
The patent leverages existing sensors in the system (such as cameras, microphones, or other sensors already present for other functionalities) and repurposes them for user presence detection in power management. By making these existing components multi-functional, the system avoids adding dedicated hardware solely for power management, thus improving power management efficiency without significantly increasing device complexity.
Data Source
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AI summary
A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., SO state) and would otherwise draw power in the SO state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.