SoC Warm Boot Peripheral Initialization Using XRAM
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Solution Overview
Problem
Existing methods fail to optimize power consumption during the warm boot process of system on chips (SoCs), leading to increased latency and power usage due to the time-consuming initialization and calibration of dynamic random-access memory (DRAM) during warm boots.
Innovation Solution
The method involves identifying interdependent hardware peripherals on the SoC, creating subsets with power consumption below a threshold, and initializing these peripherals using accelerated RAM (XRAM) before DRAM initialization, thereby optimizing power consumption by leveraging XRAM to perform selected operations during the warm boot sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM initialization and calibration is performed during warm boot, then system reliability is ensured, but power consumption increases and initialization time is extended
Solution Approach 1:
The patent applies preliminary action by performing DRAM initialization and calibration during the cold boot phase, before the system enters sleep mode. This ensures that the DRAM is fully initialized and calibrated before the warm boot sequence begins, allowing the warm boot to skip these time-consuming and power-intensive operations while maintaining system reliability.
Solution Approach 2:
The patent segments the boot process into distinct phases: cold boot with full DRAM initialization, transition to sleep mode, and warm boot that leverages the pre-initialized state. By segmenting the initialization process, the patent allows DRAM calibration to occur only when necessary (cold boot), reducing power consumption during warm boots while ensuring reliability through periodic full initialization.
2Reliability
If DRAM initialization and calibration is performed during warm boot, then system reliability is ensured, but initialization time is extended
Solution Approach 1:
The patent performs DRAM initialization and calibration as a preliminary action during cold boot, before the system enters sleep mode. This preliminary initialization remains valid during subsequent warm boots, allowing the system to skip redundant calibration steps and reduce initialization time while maintaining reliability through periodic full initialization during cold boots.
3Productivity
If XRAM is used to initialize peripherals during warm boot, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent introduces XRAM (accelerated RAM) as an intermediary storage medium between non-volatile memory and DRAM. XRAM serves as a buffer that can quickly provide data to peripherals during warm boot, improving system responsiveness. The scatter-load mechanism uses XRAM to load and execute code segments concurrently with DRAM calibration, reducing overall initialization time while managing complexity through a dedicated memory hierarchy.
Solution Approach 2:
The patent adds another dimension to the memory hierarchy by introducing XRAM as a specialized memory layer with characteristics between non-volatile memory and DRAM. This additional memory dimension enables concurrent operations (loading from XRAM while calibrating DRAM) and provides a fast intermediate storage layer that improves productivity during warm boots without requiring complete DRAM reinitialization.
Data Source
AI summary
Provided are a system and a method for optimizing power consumption in system on chip (SoC) during warm boot. The method includes identifying one or more groups of interdependent hardware peripherals on the SoC, an interdependency among at least two interdependent hardware peripherals within each group corresponding to an initialization sequence of the at least two interdependent hardware peripherals, determining power consumed by the one or more groups of interdependent hardware peripherals during the warm boot of the system, creating a subset from among the one or more groups of interdependent hardware peripherals, the power consumed during the warm boot by the one or more groups of interdependent hardware peripherals in the subset being below a power consumption threshold, and generating, based on the subset from among the one or more groups of interdependent hardware peripherals, a file with a load region and an execution region for the subset.