SoC Waveform Signatures for Faster Emulation Debug
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The time-consuming process of bringing up a hardware platform, such as an FPGA-based emulator, for verifying integrated circuit designs is hindered by limited signal visibility, implementation flaws, and difficulty in debugging functional and timing issues in System-on-Chip (SoC) designs during emulation.
Innovation Solution
A method involving the computation and comparison of signatures for both reference and emulated circuit designs at each clock cycle to detect mismatches, allowing for the identification of specific submodule failures through checksums and Boolean XOR operations, facilitating faster defect identification and compression of waveform data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FPGA-based emulation is used to verify IC designs, then verification speed is improved, but signal visibility and debugging capability deteriorate
Solution Approach 1:
The patent introduces an intermediary mechanism (signature computation and comparison system) that bridges the gap between FPGA emulation and verification. The signature generator computes compact representations of signal states, and the comparator detects mismatches between expected and actual signatures, enabling verification without direct signal probing.
Solution Approach 2:
The patent replaces the mechanical/probing-based signal observation method with a computational approach. Instead of physically probing signals or using readback mechanisms, the system uses signature computation and comparison to detect functional deviations, substituting physical measurement with mathematical transformation.
2Difficulty of detecting and measuring
If comprehensive waveform monitoring is implemented in FPGA emulation, then debugging capability is improved, but resource consumption and complexity increase
Solution Approach 1:
The patent extracts only the essential verification information needed for debugging by computing signatures from selected signal groups. Instead of monitoring all waveforms, the system extracts critical functional indicators through signature computation, reducing the information overhead while maintaining debugging effectiveness.
Solution Approach 2:
The patent transforms the verification approach by changing the parameter representation from detailed waveform data to compact signature values. This parameter transformation reduces the data dimensionality and complexity while preserving the essential functional verification capability.
3Measurement precision
If detailed signal monitoring is used to identify failure causes, then fault localization is improved, but verification time increases
Solution Approach 1:
The patent segments the verification process into two stages: rapid signature comparison for failure detection, and targeted submodule analysis for fault localization. This segmentation allows the system to quickly identify failures through signature mismatch and then focus detailed analysis only on affected submodules, reducing overall verification time while maintaining localization precision.
Solution Approach 2:
The patent performs preliminary signature computation and comparison to detect failures before detailed analysis is needed. By pre-computing signatures and comparing them against expected values, the system identifies failures early, allowing subsequent detailed analysis to be focused only on cases where failures are detected, thus reducing total verification time.
Data Source
AI summary
A method of detecting a fault in a circuit design undergoing emulation, includes in part, computing N signatures of a corresponding reference circuit design during each of the N cycles, computing N signatures of the circuit design undergoing emulation during each of the N cycles, comparing, for each of the N cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation, and detecting whether a mismatch exists between the reference circuit design signature and the signature of the circuit design undergoing emulation during each of the N cycles. The method further includes comparing the signatures of the submodules of the reference circuit design to the signatures of the corresponding submodules of the circuit design undergoing emulation to enable root causing submodule functional failures. Optionally, each signature may computed by performing a logic function on a multitude of output signals of the circuit design.