Hierarchical SoC Wrapper Cell for Simultaneous Core Testing
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Solution Overview
Problem
Conventional wrapper cells for integrated circuits, as per IEEE standard 1500, cannot simultaneously test parent and child cores in hierarchical systems, leading to increased testing time and manufacturing costs due to the need to test elements sequentially.
Innovation Solution
The improved wrapper cell design reduces the gate count and wiring complexity by using only two multiplexers and two clocking flip-flops, allowing for simultaneous testing of parent and child cores with identical circuitry for both inputs and outputs, and enabling efficient control of multiplexers to connect functional and test data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wrapper cells per IEEE standard 1500 are used, then functional elements can be tested, but parent and child cores cannot be tested simultaneously, requiring sequential testing which increases testing time
Solution Approach 1:
The wrapper cell employs dynamic multiplexing where the same physical resources (data paths, storage elements) are dynamically reconfigured between functional mode and test mode through multiplexer control signals. This allows the wrapper cell to adapt its configuration based on whether parent or child core testing is being performed, enabling simultaneous testing operations that would be impossible with static wrapper cell designs
Solution Approach 2:
The wrapper cell design provides multi-functionality by using the same data storage elements and multiplexers to serve both functional operation and test operations. The multiplexers can route signals for either normal data flow or test signal injection/extraction, allowing a single wrapper cell instance to support both parent core and child core testing functions without requiring separate dedicated test circuits
2Productivity
If wrapper cells are designed to enable simultaneous testing of parent and child cores, then testing efficiency improves, but circuit complexity increases with more multiplexers and storage elements
Solution Approach 1:
The invention merges the test functionality for both parent and child cores into a single integrated wrapper cell structure. By combining the multiplexers and storage elements into one unified cell design, the patent achieves simultaneous testing capability without proportionally increasing complexity. The shared resources are controlled through coordinated multiplexer states rather than requiring separate independent test circuits for each core
3Reliability
If more multiplexers and storage elements are added to enable simultaneous testing, then testing capability improves, but integrated circuit area increases
Solution Approach 1:
The dynamic reconfiguration capability allows the same physical hardware to serve multiple testing functions. The multiplexers dynamically switch between routing functional data and test data, enabling a single wrapper cell to support both parent and child core testing without requiring duplicate static circuit paths. This dynamic sharing significantly reduces the area compared to static designs that would need separate dedicated paths for each testing function
Data Source
AI summary
Wrapper cells for simultaneous testing of parent functional elements and child functional elements in a hierarchical SoC (System on Chip) provide a substantially reduced integrated circuit footprint by eliminating a multiplexer and providing simpler interconnections. Identical wrapper cells may be used for input and output data lines reducing the cost of the cell library.