SoC Write Clock Duty Cycle Training Circuit
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Solution Overview
Problem
The challenge lies in accurately adjusting the duty cycle of a high-speed write clock in System on Chip (SoC) for high-speed data input/output with memory devices, as existing methods fail to efficiently synchronize and calibrate the clock frequencies, leading to suboptimal performance.
Innovation Solution
The SoC incorporates a training circuit that generates and adjusts a write clock by using a mode register write command, synchronizing with a memory device's clock to calculate valid window margins and set the duty cycle to an optimal value, ensuring efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the write clock is increased for high-speed data input/output, then the data transfer speed is improved, but the duty cycle accuracy deteriorates
Solution Approach 1:
The patent performs duty cycle training before high-speed data transfer operations. The training circuit adjusts the duty cycle of the write clock in advance by sending training commands to the memory device and measuring the actual duty cycle, then applies compensation values to achieve accurate duty cycle control before actual data operations begin.
Solution Approach 2:
The patent replaces traditional hardware-based duty cycle control mechanisms with a software/firmware-based training method. Instead of relying on fixed hardware circuits to maintain duty cycle accuracy at high frequencies, the system uses programmable training sequences that can dynamically adjust and compensate for frequency-dependent duty cycle variations.
2Measurement precision
If traditional clock synchronization methods are used, then the system complexity is reduced, but the clock synchronization accuracy deteriorates
Solution Approach 1:
The patent introduces a training circuit as an intermediary component between the clock generator and the memory device. This training circuit mediates the clock synchronization process by generating training commands, receiving feedback from the memory device, and adjusting the write clock duty cycle based on measured values, thereby achieving accurate synchronization without requiring complex hardware modifications.
Solution Approach 2:
The patent implements a feedback mechanism where the training circuit sends training commands to the memory device, measures the actual duty cycle of the write clock based on received signals, calculates compensation values, and adjusts the clock parameters accordingly. This closed-loop feedback approach enables accurate clock synchronization while maintaining relatively simple system architecture.
Data Source
AI summary
A system on chip includes a first clock generator that generates a first clock to be sent to a memory device, a second clock generator that generates a second clock to be sent to the memory device, a command and address generator that generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock and generates a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device, a data receiver that receives a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock, and a training circuit that calculates a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.