SoC Write Training for Memory Signal Delay Compensation
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Solution Overview
Problem
High-speed memory devices face challenges in securing data integrity due to non-uniform synchronization parameters and varying delays in data strobe signals, particularly with fluctuations in power supply voltage.
Innovation Solution
An electronic device system-on-chip (SoC) generates data and strobe signals, and performs write training to measure and adjust delays in the data strobe signal caused by power supply voltage variations, ensuring alignment and reliability of data exchange with memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating speed of memory device is increased, then productivity is improved, but data integrity deteriorates due to non-uniform synchronization parameters and varying delays
Solution Approach 1:
The patent performs write training in advance to measure the delay of the data strobe signal at different power supply voltage levels. By pre-characterizing the delay behavior under normal and dropped voltage conditions, the system prepares compensation data before actual high-speed operation, enabling reliable data exchange even at increased operating speeds.
Solution Approach 2:
The patent changes the power supply voltage level during training operations to measure delay characteristics. By applying both normal and dropped voltage levels during training, the system captures the relationship between voltage variations and signal delay, then uses this information to adjust timing parameters during high-speed operation to maintain data integrity.
2Use of energy by moving object
If power supply voltage level is reduced to lower power consumption, then energy usage is improved, but signal delay increases due to slower signal propagation
Solution Approach 1:
The patent performs training operations at reduced power supply voltage levels in advance to measure the delay characteristics under low-power conditions. By pre-characterizing the delay behavior at dropped voltage levels, the system can compensate for the increased signal propagation time without sacrificing power efficiency during normal operation.
Solution Approach 2:
The patent uses the measured delay information from training operations as feedback to adjust the delay of the data signal. By feeding back the delay characteristics observed at different voltage levels, the system dynamically compensates for timing variations, enabling low-power operation without unacceptable signal delay penalties.
3Reliability
If write training is performed to measure and compensate signal delay, then data integrity is improved, but device complexity increases due to additional training operations
Solution Approach 1:
The patent uses the same training infrastructure and measurement mechanisms for multiple purposes: characterizing delay at normal voltage, characterizing delay at dropped voltage, and generating compensation data for high-speed operation. This multi-functional approach consolidates what could be separate complex operations into a unified training process.
Solution Approach 2:
The patent performs comprehensive delay measurements and compensation setup during initial training operations before normal high-speed data exchange begins. By completing all necessary characterization and compensation setup in advance, the actual data transfer operations can proceed without repeated complex measurements, reducing overall system complexity.
Data Source
AI summary
An electronic device includes a memory device receiving a power supply voltage, a data strobe signal, and a data signal, and a system-on-chip that exchanges data with the memory device using the data strobe signal and the data signal. The system-on-chip performs write training that measures a magnitude of a delay of the data strobe signal due to variation in the level of the power supply voltage and adjusts a delay of the data signal using a result of the write training.