Global Socket Cache Coherence via Ownership Directory
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Solution Overview
Problem
In parallel processing environments, maintaining cache coherence across multiple multicore processor chips is challenging due to different versions of memory being seen by tiles in separate chips, leading to cache coherence problems.
Innovation Solution
A method is implemented to maintain cache coherence by using an ownership directory to determine if a read request hits or misses, returning a shared status without snooping for misses, and sending a directed message to the socket with the exclusive copy of the requested line when it hits, employing an invalidate-based protocol for cache coherence across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache coherence protocols are used across multiple chips, then all tiles can access memory, but tiles in separate chips see different versions of memory leading to cache coherence problems
Solution Approach 1:
The system divides the coherence management into segments: each socket has its own directory tracking ownership of cache blocks, and the protocol operates independently within each socket while coordinating across sockets through directed messages. This segmentation allows each chip to maintain coherence independently while achieving global coherence across multiple chips.
Solution Approach 2:
The patent introduces an intermediary ownership directory mechanism that mediates cache access across multiple chips. When a cache miss occurs, the system uses the ownership directory to identify the owning socket and sends a directed message as an intermediary communication mechanism to retrieve the block, rather than using complex global snooping protocols.
2Reliability
If global snooping is used to maintain cache coherence across multiple chips, then coherence is maintained, but performance degrades due to excessive snooping and tracking overhead
Solution Approach 1:
Instead of implementing excessive global snooping across all chips for every cache access, the system applies partial action by only performing directed message exchanges with the specific owning socket identified in the ownership directory. This reduces the scope of coherence operations from global to targeted, improving performance while maintaining coherence.
Solution Approach 2:
The patent extracts the coherence management overhead from the data path by implementing an invalidate-based protocol that separates coherence validation from data access. The ownership directory tracks ownership separately, allowing the data path to proceed efficiently without extensive snooping, and coherence is maintained through targeted invalidation messages when needed.
3Productivity
If an invalidate-based protocol is used to reduce snooping overhead, then performance improves, but the complexity of tracking ownership across sockets increases
Solution Approach 1:
The ownership tracking complexity is segmented by implementing separate directory structures at each socket rather than a single global directory. Each socket's directory tracks ownership of blocks that may reside in its cache, and the inter-socket communication is segmented into directed messages to specific owners. This segmentation distributes the tracking complexity across multiple independent units.
Solution Approach 2:
The system performs preliminary action by pre-establishing the ownership directory structure and ownership relationships before cache operations begin. This preliminary organization of ownership information allows subsequent cache accesses to quickly identify the owning socket without complex real-time tracking, reducing the operational complexity of the invalidate protocol.
Data Source
AI summary
A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.