Socket Interposer Multi-Modal I/O Interface Memory Access
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Solution Overview
Problem
In multi-processor servers, leaving one CPU socket empty reduces power consumption and cost but results in inaccessible dedicated memory, limiting memory capacity for applications that require large memories but are not computation-intensive.
Innovation Solution
A socket interposer with a multi-modal I/O interface is inserted into an empty processor socket, allowing a single processor to access the dedicated memory of another processor socket, thereby extending the server's memory capacity while maintaining low latency and high interconnect bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a second CPU socket is left empty to reduce power consumption and cost, then power usage and system cost decrease, but memory capacity becomes limited because dedicated memory assigned to the empty socket becomes inaccessible
Solution Approach 1:
A socket interposer is introduced as an intermediary component that physically occupies the empty CPU socket and provides bridging circuitry. The interposer contains a multi-modal I/O interface that can operate in different modes: processor-to-processor communication mode and memory access mode. When a single CPU is installed, the interposer enables that CPU to access the dedicated memory through the interposer's I/O interface, thus mediating between the single CPU and the previously inaccessible memory resources.
Solution Approach 2:
The socket interposer's multi-modal I/O interface is designed to perform multiple functions depending on the system configuration. It can provide processor-to-processor communication when two CPUs are installed, or provide memory access when a single CPU is installed. This multi-functionality allows the same hardware component to adapt to different operational scenarios, enabling flexible resource utilization whether one or two CPUs are present in the system.
2Ease of manufacture
If a second CPU is omitted to save cost, then system cost decreases, but memory accessibility is lost
Solution Approach 1:
The socket interposer serves as a cost-effective intermediary that enables memory access without requiring a second CPU. By placing the interposer in the empty socket, the system gains the ability to access dedicated memory through the interposer's I/O interface, thus recovering memory accessibility while maintaining the cost savings of using only one CPU.
Solution Approach 2:
The multi-modal I/O interface in the interposer provides universal functionality that adapts to different system configurations. It can operate as a communication interface between processors or as a memory access interface, making the system versatile enough to support both single-CPU and dual-CPU configurations while maintaining access to all memory resources.
3Speed
If dedicated memory is assigned to each CPU socket, then memory access speed is improved, but memory utilization efficiency decreases when CPUs are omitted
Solution Approach 1:
The socket interposer acts as a mediator that maintains the direct, high-speed connection between the CPU and dedicated memory. By routing memory access requests through the interposer's I/O interface, the system preserves the low-latency, high-bandwidth characteristics of dedicated memory access while enabling a single CPU to utilize memory that was originally assigned to an empty socket, thus improving overall memory utilization efficiency.
Data Source
AI summary
Exemplary embodiments include a socket interposer having a plurality of connectors configured to attach to a server board, the server board including: a first processor socket having a processor form factor, and a first memory associated with the first processor socket, a processor inserted into the at least first processor socket, the processor having access to the first memory, and a second processor socket having the processor form factor, and a second memory associated with the second processor socket, wherein the plurality of connectors are configured to fit the processor form factor; and a multi-modal I/O interface having a first mode and a second mode, wherein in the first mode provides processor-to-processor communication, and the second mode provides the first processor with accessibility to the second memory associated with the second processor socket.