Socket Structure for Spike Current Suppression in Memory Array

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Solution Overview

Problem

Memory devices, particularly those with cross-point architectures, experience current spikes due to parasitic capacitance discharge, which can damage memory cells and lead to reliability issues like read disturb and endurance degradation.

Innovation Solution

Incorporating resistors in the access lines of memory arrays to increase resistance and suppress current spikes by screening electrical discharge from portions of the access line not being used, thereby reducing the magnitude of current spikes during memory cell selection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If resistors are incorporated in access lines to suppress current spikes, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvememory cell reliabilityVSAvoidaccess line structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the resistor structure with the existing access line architecture by forming resistive regions within the access line traces themselves, rather than adding separate discrete resistor components. This integration merges the signal transmission function with the current suppression function in a single unified structure, improving reliability while minimizing additional complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces resistive regions as intermediary elements within the access lines that act as mediators between the driver circuits and memory cells. These resistive regions suppress current spikes by providing localized resistance at critical points, protecting memory cells from harmful current transients while allowing normal operation signals to pass through

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If resistors are added to screen electrical discharge, then harmful factors are reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvecurrent spike damageVSAvoidaccess line fabrication
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent implements current suppression by changing the electrical resistance parameter of the access line at specific locations. Resistive regions are formed by modifying the cross-sectional area, material composition, or thickness of the access line traces, creating localized high-resistance zones that screen electrical discharge without requiring completely separate manufacturing processes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures in the access lines, combining conductive materials with resistive materials in specific patterns. The access lines may include layered structures or mixed-material traces where certain segments have higher resistance properties, enabling current spike suppression while maintaining overall electrical connectivity and using standard semiconductor fabrication techniques

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of resistors effectively reduces current spikes, minimizing damage to memory cells and enhancing the reliability and endurance of memory devices while maintaining normal operation capabilities.

Implementation Method 1

Incorporating resistors in the access lines of memory arrays to increase resistance and suppress current spikes

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11715520B2Socket structure for spike current suppression in a memory array
Publication Date: 2023.08.01 MICRON TECHNOLOGY INC
  • US11715520B2 patent drawing
  • US11715520B2 patent drawing
  • US11715520B2 patent drawing

AI summary

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells. To reduce electrical discharge associated with current spikes, a first resistive film is formed in the access line between the left portion and the conductive layer, and a second resistive film is formed in the access line between the right portion and the conductive layer.