Socketed Floating Gate Cells for 3D NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3D NAND memory technologies face challenges in reducing memory cell size and minimizing floating-gate perturbations between neighboring cells, which affects capacitive coupling and storage efficiency.
Innovation Solution
The implementation of a socket structure for word lines that embeds floating gates, allowing for a significant reduction in memory cell size and improved capacitive coupling, while maintaining small-cell dimensions and reducing floating-gate disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional 3D NAND memory structures are used, then memory cell size reduction is limited, but capacitive coupling and storage efficiency are compromised
Solution Approach 1:
The floating gate is embedded within a socket structure formed by the word line, creating a nested configuration where the floating gate resides inside the socket. This nesting approach allows the floating gate to be fully surrounded by the word line, maximizing capacitive coupling while minimizing the lateral footprint of each memory cell, thereby achieving both small cell size and strong capacitive coupling.
Solution Approach 2:
The invention transitions from planar capacitive coupling to three-dimensional capacitive coupling by embedding the floating gate within the socket structure. This vertical integration in the z-dimension allows for enhanced coupling between the floating gate and word line without increasing the lateral cell dimensions, effectively utilizing the third dimension to resolve the contradiction between cell size and coupling strength.
2Productivity
If memory cell dimensions are reduced, then storage density increases, but floating-gate perturbations between neighboring cells increase
Solution Approach 1:
By nesting the floating gate within the socket structure, the word line completely surrounds the floating gate laterally. This configuration provides effective electrostatic isolation between adjacent floating gates, as each floating gate is individually enclosed by its own socket. The isolation prevents charge perturbations from neighboring cells while maintaining high storage density through compact cell dimensions.
Solution Approach 2:
The socket structure provides localized electrostatic shielding around each floating gate, creating individual isolation zones. This local quality approach ensures that each memory cell is independently protected from perturbations by neighboring cells, allowing for tighter packing and higher storage density without sacrificing signal integrity or increasing cross-cell interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a 4 to 8 times reduction in cell dimension and minimizes floating-gate to floating-gate disturbances, enhancing storage efficiency and capacitive coupling in 3D NAND memory systems.
Implementation Method 1
The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate
Implementation Method 2
The floating gate of each memory cell is embedded by a socket component of a word line... having high coupling ratios
Data Source
AI summary
A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.