Soft Bit Compression Architecture for Multi-Plane Memory Reads
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Solution Overview
Problem
Current memory systems require additional reads to generate soft bit data for error correction, leading to increased power consumption and performance losses, as they often rely on hard bit data alone, which can be unreliable for memory cells with threshold voltages near the read level.
Innovation Solution
An efficient soft sense read mode is introduced, which combines hard bit and soft bit sensing into a single operation, reducing the number of reads and data transfer by shifting the read point for hard bits and using a single soft bit read for less reliable hard bit values, while compressing soft bit data before transfer to improve memory system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional reads are performed to generate soft bit data for error correction, then memory system reliability is improved, but power consumption increases
Solution Approach 1:
The patent combines hard bit sensing and soft bit sensing into a single unified read operation. The sense amplifier performs both hard bit determination (using a first read level) and soft bit generation (using a second read level) simultaneously during one read cycle, eliminating the need for separate additional reads and thereby reducing power consumption while maintaining reliability.
Solution Approach 2:
The sense amplifier is designed to perform multiple functions within a single operation: it determines hard bit values for reliable data and generates soft bit values for error correction, both during the same read cycle. This multi-functionality allows the system to achieve both reliability improvement and power reduction by avoiding redundant read operations.
2Reliability
If additional reads are performed to generate soft bit data for error correction, then memory system reliability is improved, but performance deteriorates
Solution Approach 1:
The patent merges hard bit sensing and soft bit sensing into a single read operation, reducing the total number of read cycles required. This combination eliminates the performance penalty associated with multiple sequential reads while still providing both hard bit data for direct use and soft bit data for error correction when needed.
Solution Approach 2:
The sense amplifier continuously performs both hard bit and soft bit sensing functions during a single uninterrupted read operation. This continuous action prevents performance degradation by avoiding the interruptions and delays that would result from performing separate read operations for hard bits and soft bits.
3Reliability
If soft bit data is transferred without compression, then error correction accuracy is maintained, but data transfer overhead increases
Solution Approach 1:
The patent extracts and identifies redundant or less significant bits within the soft bit data, transferring only the essential information needed for error correction. This extraction process reduces the quantity of data that must be transferred while preserving the accuracy required for effective error correction operations.
Solution Approach 2:
The patent applies compression techniques that transform the soft bit data representation, changing its parameters to reduce size. The compression maintains the critical information needed for error correction accuracy while reducing the overall data volume that requires transfer across the memory interface.
4Reliability
If multiple separate read operations are performed, then complete soft bit data is obtained, but data transfer time increases
Solution Approach 1:
The patent combines multiple read operations into a single unified read that simultaneously retrieves both hard bit data and soft bit data. This merging eliminates the sequential execution of multiple reads, thereby reducing data transfer time while ensuring that complete soft bit data is obtained for error correction purposes.
Solution Approach 2:
The sense amplifier preliminarily prepares and outputs both hard bit and soft bit data during the same read cycle, rather than requiring subsequent separate read operations. This preliminary action ensures data completeness is achieved in one operation, preventing time loss from additional reads.
Data Source
AI summary
For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.