Soft Bit Data Compression in Non-Volatile Memory Latches
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Solution Overview
Problem
Current memory systems face inefficiencies in data storage and retrieval due to the reliance on multiple reads for soft bit data, which increases power consumption and reduces performance, especially when error correction is required for unreliable hard bit values.
Innovation Solution
Implementing an efficient soft sense read mode that combines hard bit and soft bit sensing into a single operation, reducing the number of reads and data transfer by compressing soft bit data within internal data latches before transfer to the cache buffer, and reshuffling it into logical order for improved memory system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple reads are performed to retrieve soft bit data for error correction, then data reliability is improved, but power consumption increases and performance decreases
Solution Approach 1:
The patent combines hard bit sensing and soft bit sensing into a single read operation. The sense amplifier simultaneously generates both hard bit data (reliable/unreliable indicators) and soft bit data (reliability metrics) in one sensing cycle, eliminating the need for multiple separate reads and thereby reducing power consumption while maintaining data reliability
Solution Approach 2:
The patent performs soft bit sensing in advance during the same read operation that retrieves hard bit data. By generating reliability information (soft bits) during the initial sensing phase rather than requiring additional reads, the system prepares error correction data preliminarily, reducing subsequent power consumption and improving performance
2Reliability
If multiple reads are performed to retrieve soft bit data, then data reliability is improved, but memory system performance deteriorates
Solution Approach 1:
The patent merges hard bit data retrieval and soft bit data generation into a single integrated read operation. The sense amplifier produces both types of data simultaneously during one sensing cycle, eliminating the time penalty of multiple reads and thereby improving memory system performance while ensuring data reliability through comprehensive error correction information
Solution Approach 2:
The patent maintains continuous useful action by performing both hard bit sensing and soft bit generation in an uninterrupted single operation. The sensing process continuously produces reliable data and reliability metrics without idle cycles between reads, maximizing productivity while maintaining data integrity
3Quantity of substance
If soft bit data is compressed within internal data latches before transfer, then data transfer volume is reduced, but device complexity increases
Solution Approach 1:
The patent implements nested data compression by storing soft bit data within the internal data latches that already hold hard bit data. The reliability information is nested within the same latch structure, reducing external transfer volume while utilizing existing hardware resources, thereby limiting the increase in device complexity to minimal overhead
4Productivity
If hard bit and soft bit sensing are combined into a single operation, then the number of read operations is reduced, but measurement precision requirements increase
Solution Approach 1:
The patent segments the sensing output into distinct hard bit data and soft bit data components from a single sensing operation. The sense amplifier separates reliable/unreliable indicators from reliability metrics, allowing both types of data to be extracted with appropriate precision from the same sensing event, thereby reducing read operations while maintaining measurement precision through proper signal separation
Data Source
AI summary
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.