Soft-Bit Data Compression Stages for Faster NAND Transfer
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Solution Overview
Problem
The increasing data storage demands in data centers and cloud computing environments necessitate improvements in storage device performance, lifespan, and data transfer speed, particularly in semiconductor-based storage devices, where the data transfer rate between the controller and nonvolatile memory devices affects overall performance.
Innovation Solution
Incorporating a nonvolatile memory device with a compression circuit that compresses soft-bit data through multiple compression stages, controlled by a control logic circuit, to optimize data transfer and manage compression ratios dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If soft-bit data is transmitted without compression, then data transfer speed is maintained at maximum, but data transfer efficiency and storage capacity are reduced
Solution Approach 1:
The patent implements dynamic compression ratio adjustment by selectively enabling or disabling compression stages based on data characteristics and system conditions. The controller can adapt the compression level in real-time, choosing between higher compression (when time is less critical) or lower compression (when speed is prioritized), thus dynamically resolving the contradiction between transfer efficiency and transfer time.
Solution Approach 2:
The patent changes the compression parameter by providing multiple compression stages with different compression ratios. By selecting different stages or combinations of stages, the system can adjust the compression ratio to optimize the balance between data transfer efficiency and transfer time based on specific operational requirements.
2Productivity
If multiple compression stages are used, then compression efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the compression function into multiple independent compression stages, where each stage performs a portion of the overall compression task. This segmentation allows the system to achieve high compression efficiency while maintaining modularity, making the complexity manageable through staged processing rather than a single complex compression unit.
Solution Approach 2:
The compression circuit is designed with multiple stages that can be selectively activated based on requirements. The same compression circuit structure serves multiple functions: it can operate with one stage for lower complexity scenarios, or activate multiple stages for higher efficiency scenarios, making the device adaptable to different complexity requirements.
3Speed
If compression is applied to soft-bit data, then data transfer speed is improved, but processing complexity increases
Solution Approach 1:
The system dynamically adjusts the compression processing level based on the characteristics of the soft-bit data and system conditions. When data transfer speed is prioritized, the system can reduce compression processing or skip certain stages, thereby reducing processing complexity while maintaining the speed benefit where applicable.
Data Source
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AI summary
Disclosed is a storage device (20), which includes a nonvolatile memory device (200) that stores or reads user data and a controller (100) that controls the nonvolatile memory device (200), and the nonvolatile memory device (200) includes a memory cell array (220) including a plurality of memory cells that stores data bits corresponding to the user data, a compression circuit (260) that compresses soft-bit data (SBD) sensed from the plurality of memory cells, and control logic circuit (210) that controls the compression circuit (260) through a plurality of compression stages (ST1_1, ST_2) and transmits a stage control signal (SCS) to the compression circuit (260) to control whether compression on each of the plurality of compression stages (ST1_1, ST_2) is performed.