Soft Bit Compression for Data Storage Error Correction

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Solution Overview

Problem

The generation and use of soft bits in non-volatile storage devices consume resources and reduce performance due to the need for additional sensing operations and increased system bandwidth, as they are used to improve error correction capabilities but require significant data transfer and processing.

Innovation Solution

A data storage device compresses soft bits using a lossy compression technique, reducing the number of soft bits transferred from the memory to the controller, and employs a three-stage decoding process to compensate for the loss of information, utilizing AND operations to generate a second set of soft bits with a lower bit count for use in error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If soft bits are generated and transferred to improve error correction capability, then reliability is improved, but device complexity and resource consumption increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidsensing operations and data transfer
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of soft bit representation by encoding multiple soft bits into a compressed format with fewer bits. Instead of transferring the full soft bit information, the system transforms the data representation to achieve the same error correction capability with reduced bandwidth and complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts only the essential error correction information from the full soft bit data and transfers only that compressed portion to the controller. This extraction approach maintains the necessary reliability while eliminating redundant data transfer.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If soft bits are transferred from memory to controller, then error correction capability is improved, but system bandwidth is reduced for other operations

Engineering Contradiction:
Improveerror correction capabilityVSAvoidsystem bandwidth availability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent transforms the soft bit data from its original high-bit format into a compressed low-bit representation, changing the data parameter to reduce the volume transferred over the bus, thereby freeing system bandwidth for other operations while preserving error correction functionality.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent transfers only the necessary portion of soft bit information required for error correction rather than the complete soft bit dataset. This partial action approach provides sufficient error correction capability without the excessive bandwidth consumption of full soft bit transfer.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If additional sensing operations are performed to generate soft bits, then error correction capability is improved, but resource consumption and processing time increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts only the critical error correction information from the sensing operations and compresses it for transfer. This extraction eliminates the need to process and transfer all sensed data, reducing processing time while maintaining error correction capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transforms the sensed soft bit data into a compressed parameter representation that requires less processing and transfer time, thereby reducing the loss of time while preserving the essential error correction information.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10474525B2Soft bit techniques for a data storage device
Publication Date: 2019.11.12 SANDISK TECHNOLOGIES LLC
  • US10474525B2 patent drawing
  • US10474525B2 patent drawing
  • US10474525B2 patent drawing

AI summary

A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.