Soft Bit Data Compression in Non-Volatile Memory Latches
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Solution Overview
Problem
Current memory systems face inefficiencies in data storage and retrieval due to the high power consumption and performance overhead associated with using soft bit data for error correction, particularly in non-volatile memory technologies like NAND flash memory, where soft bit data requires additional reads and transfers, leading to increased energy usage and processing time.
Innovation Solution
Implementing an efficient soft sense mode that combines hard bit and soft bit sensing into a single operation, reducing the number of reads needed and compressing soft bit data before transfer, thereby minimizing data transfer and processing overhead, and utilizing a network-on-chip (NOC) architecture for improved communication efficiency within the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft bit data is used for error correction in non-volatile memory, then error correction reliability is improved, but power consumption increases and processing time increases
Solution Approach 1:
The patent extracts only the necessary soft bit information needed for error correction and transfers only this compressed data to the error correction circuitry, rather than transferring all raw soft bit data. This reduces the data transfer volume and associated power consumption while maintaining the reliability benefits of soft bit error correction.
Solution Approach 2:
The patent applies compression algorithms that transform soft bit data from its original format into a compressed representation, changing the data parameters (size, format) while preserving the essential error correction information. This parameter transformation reduces the amount of data that needs to be processed and transferred, thereby reducing power consumption.
2Reliability
If soft bit data is used for error correction in non-volatile memory, then error correction reliability is improved, but processing time increases
Solution Approach 1:
The patent performs soft bit sensing and compression in advance during the read operation, preparing the compressed soft bit data before it is needed by the error correction circuitry. This preliminary action eliminates the need for additional processing time during error correction, as the data is already prepared and compressed.
Solution Approach 2:
By extracting only the essential soft bit information through compression, the patent reduces the volume of data that requires processing. This extraction of necessary information while discarding redundant data decreases the processing time required for error correction operations.
3Reliability
If soft bit data is transferred to error correction circuitry, then error correction capability is improved, but data transfer overhead increases
Solution Approach 1:
The patent transforms the soft bit data through compression, changing its size and format parameters. This compression reduces the data transfer overhead by minimizing the amount of data that needs to be moved across the memory interface and processed by the error correction circuitry.
Solution Approach 2:
The patent introduces a compression mechanism as an intermediary between the memory array and the error correction circuitry. This intermediary processes the soft bit data, compressing it before transfer, thereby reducing the burden on the data transfer infrastructure and associated overhead.
Data Source
AI summary
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.