De-Rate Matching of Soft Bits With Direct Addition and Low Latency

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Solution Overview

Problem

The existing de-rate matching processes in mobile communication networks require high memory usage and processing latency, reducing resource utilization efficiency and communication rate.

Innovation Solution

A method and apparatus for de-rate matching that directly adds E soft bits from demodulation to generate Z soft bits without de-interleaving and reorganization, utilizing a buffer device for direct additions and incorporating pipeline processing to reduce memory and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional de-rate matching processes are used, then accurate bit restoration is achieved, but memory usage and processing latency increase

Engineering Contradiction:
Improvebit restoration accuracyVSAvoidprocessing latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts and eliminates the de-interleaving and reorganization steps from the traditional de-rate matching process. By directly adding E soft bits from demodulation to generate Z soft bits without these intermediate steps, the invention reduces processing latency while maintaining bit restoration accuracy through the direct mathematical relationship between the bits.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges multiple traditional processing steps (de-interleaving, reorganization, and bit restoration) into a single direct addition operation. By combining these operations into one step where E soft bits are directly added to generate Z soft bits, the invention reduces both processing latency and memory usage while preserving the essential function of bit restoration.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If traditional de-rate matching processes are used, then complete bit processing is achieved, but memory usage increases

Engineering Contradiction:
Improveprocessing completenessVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent removes the de-interleaving and reorganization steps that require significant memory resources. By eliminating these intermediate processing stages and directly adding soft bits, the invention reduces memory usage while maintaining processing completeness through the direct mathematical transformation from E soft bits to Z soft bits.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines multiple memory-intensive operations into a single direct addition step. By merging de-interleving, reorganization, and bit restoration into one operation where E soft bits are directly added to generate Z soft bits, the invention significantly reduces memory requirements while preserving the complete processing function.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12634036B2Methods and apparatuses for facilitating de-rate matching of bits of transmitted symbols formed after a rate matching procedure
Publication Date: 2026.05.19 HONG KONG APPLIED SCI & TECH RES INST
  • US12634036B2 patent drawing
  • US12634036B2 patent drawing
  • US12634036B2 patent drawing

AI summary

The present disclosure proposes a method used by a receiver for facilitating de-rate matching of bits of symbols formed after a rate matching procedure from a transmitter, wherein the transmitter selected Z bits from channel-coded bits, and then generated E bits by concatenation of the Z bits and their copies for the rate matching procedure. The method facilitates the de-rate matching by directly adding E soft bits from the demodulation in a particular manner to generate the Z soft bits, thus reducing memory usage and processing latency required by the de-rate matching.