Soft Bit Data Latch Compression for Non-Volatile Memory Reads
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Solution Overview
Problem
Current memory systems require additional reads to generate soft bit data, leading to increased performance and power consumption, and often rely on hard bit data alone, which can be unreliable for memory cells with threshold voltages near the read level.
Innovation Solution
An efficient soft sense read mode that combines hard bit and soft bit sensing into a single operation, reducing the number of reads and data transfer by shifting the hard bit read point and using a single soft bit read for less reliable hard bit values, and compressing soft bit data before transfer to improve memory system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional reads are performed to generate soft bit data, then memory system reliability is improved, but power consumption and performance increase
Solution Approach 1:
The patent combines hard bit sensing and soft bit sensing into a single read operation. The sense amplifier performs both types of sensing simultaneously by using different reference voltages for different memory cells connected to the same bit line, eliminating the need for separate read operations and thereby reducing power consumption while maintaining reliability improvements.
Solution Approach 2:
The patent applies soft bit sensing selectively only to memory cells that require it (those with threshold voltages near the read level), rather than performing soft bit sensing on all memory cells. This partial application reduces the overall power consumption and performance impact while still providing reliability improvements where needed.
2Reliability
If additional reads are performed to generate soft bit data, then memory system reliability is improved, but performance decreases
Solution Approach 1:
The patent merges hard bit and soft bit sensing operations into a single read cycle. By configuring the sense amplifier to perform both sensing types simultaneously using different reference voltages, the system obtains both hard bit and soft bit data without increasing the number of read operations, thereby maintaining performance while improving reliability.
Solution Approach 2:
The patent implements soft bit sensing only for memory cells that benefit from it (those with ambiguous threshold voltages), rather than applying it universally. This selective approach reduces the computational and data transfer overhead associated with soft bit processing, thereby minimizing performance impact while still achieving reliability improvements.
3Measurement precision
If soft bit data is transferred without compression, then data accuracy is maintained, but data transfer volume increases
Solution Approach 1:
The patent extracts and transfers only the essential reliability information from the soft bit data rather than transferring all raw soft bit data. By identifying and transferring only the critical reliability metrics needed for error correction, the system maintains data accuracy while significantly reducing the data transfer volume.
Solution Approach 2:
The patent transforms the soft bit data from its original form into a compressed representation that retains the essential reliability information. By changing the parameter representation (e.g., using compressed formats or selective data retention), the system maintains measurement precision while reducing the quantity of data that needs to be transferred.
Data Source
AI summary
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.