Soft-Bit Memory Reading for LDPC Error Correction Convergence
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices, such as flash memory, often experience erroneous data due to noise and charge neutrality over time, leading to corrupted data bits during read operations, necessitating effective error correction mechanisms.
Innovation Solution
The use of iterative probabilistic decoding with low density parity check codes and logarithmic likelihood ratios (LLRs) for error correction, along with soft bit reading at multiple compare levels to improve decoding convergence and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used, then the device complexity is low, but the reliability of data reading deteriorates due to noise and charge neutrality over time
Solution Approach 1:
The patent changes the parameter of read resolution from traditional hard bit reading to soft bit reading with multiple compare levels. By reading at multiple voltage thresholds (e.g., V1, V2, V3 for a 3-bit cell), the system obtains multiple reliability metrics for each bit, transforming the reading parameter to achieve better error correction capability without requiring fundamentally new hardware architectures
Solution Approach 2:
The patent adds a new dimension to error correction by introducing probabilistic decoding in the logarithmic likelihood ratio domain. Instead of simple binary hard decisions, the system operates in a continuous probability space, adding a dimensional transformation that enables more sophisticated error correction while maintaining compatibility with existing memory cell structures
2Measurement precision
If soft bit reading at multiple compare levels is implemented, then the measurement precision of memory cell states is improved, but the loss of time increases due to multiple read operations
Solution Approach 1:
The patent performs preliminary probabilistic decoding using initial reliability metrics before completing all soft bit reads. By attempting convergence with available data and only reading additional soft bits if needed, the system prepares and acts in advance to avoid unnecessary read operations, thereby reducing the time penalty while maintaining high measurement precision when required
3Reliability
If iterative probabilistic decoding is used, then the reliability of error correction is improved, but the device complexity increases due to complex decoding algorithms
Solution Approach 1:
The patent implements feedback-based iterative decoding where reliability metrics are continuously updated based on parity check results. The decoding process uses feedback from convergence status to dynamically adjust reading operations - if convergence is achieved early, additional reads are cancelled; if not, more soft bits are read. This feedback mechanism improves reliability while managing complexity through adaptive control
Data Source
AI summary
Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.