Soft Bit Reference Level Calibration for Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory systems face challenges in error correction due to variations in sensed states from written states, leading to data errors, which existing hard bit reference levels are insufficient to address effectively.
Innovation Solution
Calibration of soft bit reference levels is implemented by sensing non-volatile memory cells at both hard and test soft bit reference levels, determining metrics based on bin counts and unsatisfied counters, to establish new soft bit reference levels that maximize mutual information and improve error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard bit reference levels are used for sensing memory cells, then the sensing process is simple and fast, but error correction capability is insufficient due to lack of reliability information
Solution Approach 1:
The sensing process is segmented into multiple reference level measurements (hard bit reference level and multiple soft bit reference levels) to extract different types of information. Hard bit sensing provides binary decisions while soft bit sensing at multiple levels provides reliability metrics, allowing the system to process information in segments rather than requiring a single complex sensing operation.
Solution Approach 2:
The patent transitions from one-dimensional hard bit sensing (single reference level, binary output) to multi-dimensional soft bit sensing (multiple reference levels, multi-level output). By adding the dimension of multiple reference levels (Vr1, Vr2, ..., Vr7) and corresponding soft bit outputs, the system gains additional information about signal reliability without fundamentally changing the sensing hardware architecture.
2Reliability
If soft bit reference levels are used for sensing memory cells, then error correction capability is improved through reliability information, but the sensing process becomes more complex and time-consuming
Solution Approach 1:
The patent performs preliminary sensing operations at multiple soft bit reference levels before final decoding. By pre-collecting soft bit information from multiple reference levels (Vr1-Vr7) and calculating reliability metrics in advance, the system prepares optimized input data for the decoder, reducing the time required during actual read operations and enabling faster error correction decisions.
Solution Approach 2:
The sensing process maintains continuous useful action by overlapping measurement phases. While memory cells are being sensed at one reference level, preparation for the next reference level measurement is initiated, and decoding operations begin as soon as sufficient soft bit information is collected. This continuous pipeline approach minimizes idle time and reduces overall sensing duration despite multiple reference levels.
3Measurement precision
If multiple test soft bit reference levels are used for calibration, then the accuracy of soft bit reference levels is improved, but the calibration process becomes more complex
Solution Approach 1:
The calibration process uses feedback from decoding performance to iteratively optimize soft bit reference levels. The system measures decoding success rates and error correction performance at different reference level configurations, then adjusts the reference levels (Vr1-Vr7) based on this feedback. This closed-loop approach systematically improves reference level accuracy while providing guidance on which calibration parameters to adjust, reducing the complexity of exploring all possible configurations.
Solution Approach 2:
The patent systematically varies calibration parameters (reference voltage levels, bin thresholds, soft bit weighting factors) to find optimal configurations. By changing parameters in a structured manner and measuring performance impact, the calibration process transforms a complex multi-parameter optimization problem into a series of manageable parameter adjustments, each improving reference level accuracy based on previous results.
Data Source
AI summary
Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.