Soft Bit Viterbi Equalization With Partially Collapsed Metrics
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Solution Overview
Problem
Existing Viterbi equalizers face challenges in minimizing symbol error rates due to the high complexity of the Viterbi Algorithm, especially in 8-PSK modulation for EDGE systems, where the large number of states required makes computational complexity prohibitive, and existing Reduced State Sequence Estimators (RSSE) have poorer soft decision performance compared to hard decision performance.
Innovation Solution
A Soft Bit Viterbi Equalizer (SBVE) is introduced, which uses partially collapsed and completely collapsed bidirectional cumulative metrics to improve soft decision performance, reducing computational overhead and achieving significant reductions in block error rates by adapting the Viterbi Algorithm for 8-PSK modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Maximum Likelihood Sequence Estimator (MLSE) based on Viterbi Algorithm is used for 8-PSK modulation, then symbol error rate is minimized, but computational complexity becomes prohibitive due to large number of states (512 to 4096 states)
Solution Approach 1:
The patent segments the complex 8-PSK modulation problem into multiple QPSK sub-problems. By decomposing the 8-PSK constellation into multiple QPSK constellations and processing them separately through parallel Viterbi equalizers, the state complexity is reduced from 512-4096 states to manageable levels while maintaining near-optimal performance through coordinated processing of sub-constellations
Solution Approach 2:
The patent applies partial action by using Reduced State Sequence Estimator (RSSE) techniques that process only a subset of the full state space. The equalizer processes selected sub-constellations and uses decision feedback to compensate for the reduced state processing, achieving acceptable performance with significantly reduced computational complexity
2Device complexity
If Reduced State Sequence Estimator (RSSE) is used to reduce computational complexity, then device complexity is reduced, but soft decision performance deteriorates compared to hard decision performance
Solution Approach 1:
The patent introduces decision feedback mechanisms where hard decisions from the Viterbi equalizer are fed back to refine soft decision metrics. The equalizer uses the detected symbol decisions to update the channel state and recalculate likelihood values, thereby improving soft decision performance despite the reduced state processing capability of RSSE
Solution Approach 2:
The patent introduces an intermediary processing stage that bridges the gap between hard decision Viterbi equalization and soft decision requirements. The system uses the hard decisions as intermediate results and applies additional processing layers including metric refinement and probability calculation to generate accurate soft decisions for forward error correction
Data Source
AI summary
First and second partially collapsed metric values are determined for each bit in a symbol transition. Each first partially collapsed metric value is a cumulative metric of starting in a first state and ending in a second state in L transitions with the respective bit in the symbol transition being a first value. Each second partially collapsed metric value is a cumulative metric of starting in the first state and ending in the second state in L transitions with the respective bit in the symbol transition being a second value, the second value differing from the first value. For each bit in the symbol transition, a relative likelihood value is determined based on its respective first and second partially collapsed metric values. A symbol is decoded based on a hard decision performed using the relative likelihood value for each bit in the symbol transition.