Soft Chipkill Recovery for NAND Bitline Failure Correction
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Solution Overview
Problem
Current chipkill error correction schemes face challenges in effectively recovering from bitline failures in non-volatile memory devices, particularly in NAND flash memory, due to the difficulty in detecting and correcting multiple bitline failures.
Innovation Solution
The implementation of soft chipkill recovery methods that generate chipkill parities based on diagonally positioned symbols across codewords, allowing for robust detection and correction of bitline failures by distributing information across multiple parity bits and using soft information to identify candidate bitlines for failure, thereby improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chipkill error correction schemes are used, then single memory chip failure can be protected, but multiple bitline failures cannot be effectively detected and corrected
Solution Approach 1:
The patent segments the error correction approach by dividing the memory block into multiple codewords and introducing an additional parity codeword specifically dedicated to detecting and correcting bitline failures. This segmentation allows the system to handle different types of failures (single chip vs. multiple bitlines) with specialized correction mechanisms.
Solution Approach 2:
The patent adds a new dimension to the error correction scheme by introducing a parity codeword that spans across multiple data codewords. This additional dimension enables the detection and correction of multiple bitline failures that traditional single-chip-focused schemes cannot handle.
2Reliability
If soft chipkill recovery methods are implemented, then multiple bitline failures can be detected and corrected, but decoding complexity increases
Solution Approach 1:
The patent performs preliminary action by generating the parity codeword in advance during the encoding phase. This parity codeword is then used during decoding to identify candidate bitlines that may have failed, simplifying the overall decoding process by pre-processing error detection information.
Solution Approach 2:
The patent implements feedback by using the parity codeword to provide information about potential bitline failures during the decoding process. This feedback mechanism allows the decoder to adjust its operations and focus computational resources on correcting identified errors rather than attempting to correct all possible errors simultaneously.
3Measurement precision
If parity codeword is generated based on diagonally positioned symbols, then bitline failure detection is improved, but encoding complexity increases
Solution Approach 1:
The patent applies asymmetry by generating the parity codeword based on diagonally positioned symbols rather than symmetric row-by-row or column-by-column positioning. This asymmetric approach improves the distribution of error information across the parity codeword, enhancing the ability to detect and locate bitline failures.
Data Source
AI summary
Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.