Soft CPU Configuration in Vehicle ECUs for FPGA Area Utilization

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Solution Overview

Problem

Electronic control units for vehicles face inefficiencies in utilizing programmable logic modules with soft CPUs, particularly due to unused remaining area, which limits the flexibility and increases development costs as the complexity of test setups and execution decreases with progressing development stages.

Innovation Solution

A method involving processor-in-the-loop simulations to create and test various soft CPU configurations and model variants, optimizing the programmable logic module's area usage by determining the optimal configuration based on profiling data, allowing for efficient use of remaining space and resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a soft CPU is configured on a programmable logic module, then processing flexibility and functionality are improved, but unused residual area increases reducing resource utilization efficiency

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidunused residual area
Core Design Contradiction:
Adaptability or versatilityVSLoss of substance

Solution Approach 1:

The patent implements multiple different soft CPU configurations on the same programmable logic module, where each configuration serves different processing requirements. The system can dynamically select and switch between different CPU configurations (e.g., different instruction sets, different operational modes) to handle various computational tasks, thereby making the hardware resource universally applicable to multiple functions and reducing wasted capacity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If multiple soft CPU configurations are tested through processor-in-the-loop simulations, then optimal configuration identification is improved, but test setup complexity and development time increase

Engineering Contradiction:
Improveconfiguration optimization accuracyVSAvoidtest setup complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the comprehensive testing process into segmented, modular simulation scenarios. Each processor-in-the-loop simulation tests a specific configuration aspect (e.g., floating-point performance, integer operations, memory access patterns) independently. This segmentation allows systematic evaluation of multiple configurations without requiring a monolithic complex test setup, as each segment can be developed, executed, and analyzed separately then combined for overall optimization determination.

Inventive Principle:
Principle #1Segmentation

3Productivity

If processor-in-the-loop simulations are conducted for multiple configurations, then resource utilization optimization is improved, but computational overhead and execution time increase

Engineering Contradiction:
Improveresource utilization efficiencyVSAvoidsimulation execution time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent employs a staged simulation approach where not all possible soft CPU configurations are tested to full completion. Instead, initial simulations identify promising configurations, then subsequent simulations focus only on those candidates. This partial action strategy reduces total simulation time by avoiding exhaustive testing of all configurations, while still achieving sufficient optimization accuracy for practical deployment.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP2899652B1Method for optimising the operation of programmable logic modules in control devices for vehicles
Publication Date: 2024.03.13 DSPACE DIGITAL SIGNAL PROCESSING & CONTROL ENGINEERING GMBH
  • EP2899652B1 patent drawingFigure 1

AI summary

The invention relates to a method and a system for optimizing the use of a programmable logic module for use in an electronic control unit for vehicles, wherein the programmable logic module has a soft CPU and/or an unused residual area.The task is solved by creating a large number of model variants that represent the functionality of the control unit, and by creating a large number of soft-CPU configurations with different configuration scopes that occupy an area of ​​the programmable logic block corresponding to the configuration scope, and by performing processor-in-the-loop simulations for the large number of model variants and/or soft-CPU configurations after instantiating the soft-CPU according to the soft-CPU configuration on a programmable logic block, and by using the profiling data of the soft-CPU generated during the PIL simulation with regard to the processing of the input signal to optimize the use of the programmable logic block.