Soft Decision Data Compression for Faster NAND Error Correction
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Solution Overview
Problem
Non-volatile memory devices face challenges in efficiently correcting errors in data due to overlapping threshold voltage distributions, leading to high error rates in hard decision data, especially when distributions degrade over time.
Innovation Solution
A memory device and method that compresses soft decision data by encoding the location of '1' bits, allowing parallel output of hard decision data and compressed soft decision data, reducing read time and improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft decision data is read using multiple soft read voltages to improve error correction, then error correction capability is improved, but read time increases
Solution Approach 1:
The soft decision data is divided into multiple groups based on voltage levels (first group with first voltage level, second group with second voltage level). This segmentation allows parallel processing of different voltage groups, reducing the overall read time while maintaining comprehensive error correction capability through soft decision information from all groups.
Solution Approach 2:
Hard decision data is read and output first before the soft decision data compression is completed. This preliminary action allows the hard decision data to be available immediately for initial processing, while the compressed soft decision data is prepared in parallel and output subsequently, optimizing the overall read timeline.
2Productivity
If soft decision data is compressed by encoding location of '1' bits to reduce data volume, then data transmission efficiency is improved, but compression complexity increases
Solution Approach 1:
The compression circuit extracts and encodes only the locations of bits with value '1' in the soft decision data, rather than processing all bits. This selective extraction significantly reduces the amount of data that needs to be compressed and transmitted, improving data transmission efficiency while keeping the compression logic relatively simple.
Solution Approach 2:
The patent uses a standardized encoding scheme where locations of '1' bits are represented using a consistent format (e.g., using two bits per location: 00 for '0', 01 for first '1', 10 for second '1'). This standardized copying approach simplifies the compression circuit design by providing a regular, predictable encoding pattern that is easy to implement and decode.
3Reliability
If hard decision data and soft decision data are read separately to ensure data accuracy, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent merges the reading operations for hard decision data and soft decision data into a unified process. Both types of data are read from the same memory cell array using different voltage levels in an integrated manner, with coordinated output timing. This merging ensures data integrity through proper sequencing while reducing total processing time compared to completely separate read operations.
Solution Approach 2:
The reading and outputting of hard decision data and soft decision data are performed in continuous operation without idle gaps. While hard decision data is being output, the compression of soft decision data is being performed in parallel, and both operations complete in sequence without interruption, maintaining continuous useful action throughout the read process.
Data Source
AI summary
A memory device includes a first memory cell array and a second memory cell array, a first page buffer and a second page buffer configured to read data from the first memory cell array and the second memory cell array, respectively; and a first compression circuit configured to compress first soft decision data into first compressed data by encoding a location of a bit having a first value among bits of the first soft decision data, the first soft decision data being obtained from the first memory cell array by using a plurality of soft read voltages, wherein the first compression circuit is further configured to compress the first soft decision data into the first compressed data while second hard decision data is being output, the second hard decision data being read from the second memory cell array by using a hard read voltage.