Soft Decision Value Circuit Using Phase Rotation and Min Selection
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Solution Overview
Problem
Existing soft decision value generation circuits for differentially encoded modulation schemes, such as DEQPSK, require large circuit scales and high power consumption due to extensive calculation and hardware needs for generating soft decision values, particularly when implemented in digital circuits or FPGAs.
Innovation Solution
A soft decision value generation circuit that includes phase rotation, addition, minimum value selection, and sign reflection units to calculate soft decision values with reduced arithmetic operations, thereby minimizing calculation and hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the general principle of soft decision value calculation is applied to DEQPSK, then soft decision values can be generated, but the circuit scale and power consumption become large due to extensive calculation requirements
Solution Approach 1:
The patent segments the soft decision value calculation into two independent parts: real component calculation and imaginary component calculation. Each component is processed separately through its own set of calculation units, avoiding the need to process all 8 modulation symbol candidates simultaneously for both components. This segmentation reduces the circuit scale while maintaining calculation accuracy.
Solution Approach 2:
The patent calculates soft decision values for only 4 out of the 8 possible modulation symbol candidates by exploiting the symmetry properties of DEQPSK modulation. Specifically, it calculates values for candidates where the bit value matches the received signal's phase quadrant, and uses symmetry relationships to derive the other values, thereby reducing computational complexity while maintaining sufficient accuracy.
2Measurement precision
If the general principle of soft decision value calculation is applied to DEQPSK, then soft decision values can be generated, but power consumption increases due to extensive calculation
Solution Approach 1:
By segmenting the calculation into separate real and imaginary component processing paths, the patent enables independent and parallel computation that reduces total calculation cycles. Each segment processes fewer candidates, directly reducing the energy consumed by arithmetic operations in the circuit.
Solution Approach 2:
The patent performs partial calculation by computing soft decision values for only 4 candidates instead of all 8, using symmetry properties to derive the remaining values. This partial computation approach significantly reduces the number of arithmetic operations and associated power consumption while maintaining acceptable accuracy for error correction decoding.
3Productivity
If multiple circuits operate in parallel using the general soft decision value generation method, then processing capacity increases, but circuit scale and power consumption increase proportionally
Solution Approach 1:
The patent structures the circuit with segmented calculation units for real and imaginary components that can be efficiently replicated and operated in parallel. Each parallel unit processes a subset of candidates, allowing multiple units to work simultaneously with reduced individual complexity, achieving high processing capacity without linearly increasing total circuit scale.
Data Source
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AI summary
Provided is a soft decision value generation circuit capable of reducing the amount of calculation and the hardware scale for generating a soft decision value. The soft decision value generation circuit includes: a phase rotation unit (2) for rotating phases of received symbols after coherent detection; addition units (3a, 3b) for calculating, by using the phase-rotated received symbols, absolute values of soft decision values for soft decision value candidates restricted in advance; minimum value selection units (4a, 4b) for selecting minimum values out of the absolute values of the soft decision values; sign reflection units (5a, 5b) for reflecting, based on the phases of the received symbols after the phase rotation, sign information to the minimum values; and soft decision value correction units (6a, 6b) for multiplying outputs of the sign reflection units (5a, 5b) by a coefficient depending on a noise variance value and an amplitude value of a modulation symbol.