Soft Decoding Error Prediction in NAND Memory
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Solution Overview
Problem
Existing schemes fail to precisely predict soft decoding failures in memory systems, which is crucial for defense and media management algorithms, especially in penta-level cell NAND systems where soft decoding is used for all read traffic.
Innovation Solution
A novel scheme predicts soft decoding failure by considering the entire log likelihood ratio (LLR) distribution, using a two-dimensional table that correlates fail bit count (FBC), strong correct rate, and spare byte size to determine soft decoding error probabilities, allowing for more accurate prediction of soft decoding failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing error prediction schemes are used, then the system is simple to operate, but the prediction accuracy of soft decoding failures is insufficient
Solution Approach 1:
The patent transitions from one-dimensional error prediction (using only fail bit count) to two-dimensional prediction by incorporating both fail bit count and strong correct rate as independent dimensions. This dimensional expansion enables the system to capture the complex relationship between different error types and their impact on soft decoding failure, thereby improving prediction accuracy without requiring complete system redesign.
Solution Approach 2:
The patent segments the error analysis into distinct components: fail bit count (FBC) representing decoding failures, strong correct rate (SC) representing correctable errors, and spare byte information. By dividing the error prediction problem into these segmented components, the system can process and analyze each aspect independently before combining them for comprehensive prediction, maintaining operational simplicity while enhancing accuracy.
2Speed
If soft decoding is used for all read traffic in penta-level cell NAND systems, then the data access speed is improved, but the occurrence of soft decoding failures increases
Solution Approach 1:
The patent implements feedback mechanisms by continuously monitoring fail bit count and strong correct rate during decoding operations. This feedback information is used to update the error prediction model, allowing the system to adapt to changing decoding conditions and predict soft decoding failures more accurately, thereby enabling better control of the decoding process and improvement of overall reliability.
Solution Approach 2:
The patent performs preliminary analysis by calculating fail bit count and strong correct rate before final decoding decisions are made. This preliminary action allows the system to predict potential soft decoding failures in advance and take preventive measures, such as adjusting decoding parameters or triggering error correction routines, thereby reducing the actual failure rate while maintaining high data access speed.
Data Source
AI summary
A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: read and decode codewords from the memory block, determine a fail bit count (FBC), a strong correct (SC) rate indicating a percentage of failed bits correctable through log likelihood ratios (LLRs), and a number of spare bytes in the codewords decoded from the memory, predict a soft decoding error based on a fixed FBC, a fixed SC rate, and the number of spare bytes, and determine soft errors in the codewords read from the memory block based on the predicted soft decoding error.