Soft Defect Localization in Semiconductor Chips Using Segmented Laser Scanning
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Solution Overview
Problem
Conventional semiconductor chip testing methods, such as pixel-by-pixel laser scanning, are time-consuming and inefficient, requiring hours or days to locate soft defects due to the need to test each pixel individually, which can lead to smearing of signals and limited analysis of critical timing paths.
Innovation Solution
Applying an external stimulus to larger fractional portions of the semiconductor chip's surface, such as halves or quadrants, to quickly identify soft defects, followed by more focused testing on identified areas, using a shutter system to selectively expose and perturb portions of the chip with infrared radiation while running test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel-by-pixel laser scanning is used to test each pixel individually, then measurement precision of soft defect location is improved, but loss of time increases significantly
Solution Approach 1:
The chip surface is divided into multiple regions of interest (ROIs) rather than testing pixel-by-pixel. The method segments the testing process into two stages: first identifying candidate ROIs using efficient algorithms, then performing detailed pixel-by-pixel testing only within those segmented regions. This reduces the total number of pixels tested while maintaining defect localization precision.
Solution Approach 2:
Before performing time-consuming pixel-by-pixel testing, the method performs preliminary actions by first identifying candidate regions of interest using efficient algorithms that analyze chip characteristics and predict potential defect locations. This preliminary segmentation allows subsequent detailed testing to be focused only on relevant areas, significantly reducing overall testing time while maintaining precision.
2Reliability
If long and complex test patterns are used to exercise circuits fully, then reliability of defect detection is improved, but loss of time increases
Solution Approach 1:
Different test patterns are applied to different regions of interest based on their specific characteristics. Rather than using a single long complex test pattern for the entire chip, the method selects and applies appropriate test patterns locally to each ROI, exercising circuits sufficiently to detect defects while minimizing unnecessary testing time.
Solution Approach 2:
The method applies test patterns selectively to candidate regions of interest rather than to the entire chip. This partial action approach uses sufficient testing coverage to detect defects in the identified ROIs without the time penalty of testing all pixels with long complex patterns, achieving adequate reliability for defect detection in a reduced time frame.
3Measurement precision
If the laser spot dwells on each pixel for sufficient time for signal detection, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The testing process is segmented into two phases: rapid identification of candidate ROIs using efficient algorithms, followed by detailed signal detection only within those segmented regions. This segmentation allows sufficient dwell time for signal detection in the ROI phase while maintaining high productivity through the efficiency of the initial identification phase.
Solution Approach 2:
The method performs preliminary identification of candidate regions using algorithms that quickly analyze chip characteristics and predict defect locations. This preliminary action enables subsequent signal detection to be performed with sufficient dwell time only in the identified ROIs, rather than requiring long dwell times across all pixels, thus maintaining measurement precision while improving overall productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces testing time by allowing rapid detection and localization of soft defects, enabling more efficient use of pixel-by-pixel testing on smaller, previously identified areas, thereby speeding up the defect identification process.
Implementation Method 1
The basic setup for these techniques uses a constant current source for biasing the device under test and a detector to sense the change in the voltage demand due to the localized heating
Implementation Method 2
Light Induced Voltage Alteration (LIVA)
Data Source
AI summary
Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.