Soft Erase Method for Nonvolatile Memory Read Disturbance
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Solution Overview
Problem
Nonvolatile memory devices, particularly those with three-dimensional memory cell arrays, face challenges in improving data program and read operation performance due to issues like hot carrier injection and read disturbance, which affect the reliability and efficiency of data storage.
Innovation Solution
A soft erase method is introduced that involves applying pre-pulses to string select transistors of unselected memory cell strings during verification intervals, along with a turn-on voltage to selected memory cell strings, to manage potential differences and reduce hot carrier injection, thereby enhancing the programming state verification and data read accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory cell array is used to increase storage capacity, then the storage density is improved, but hot carrier injection and read disturbance occur affecting reliability
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block containing multiple memory cell strings. This segmentation allows selective erasure of specific blocks without affecting others, enabling targeted reliability improvement while preserving overall storage capacity. The block-level management facilitates precise control over which regions undergo soft erase operations.
Solution Approach 2:
A soft erase operation is performed as a preliminary action before normal programming operations. This preliminary soft erase reduces the threshold voltage of memory cells in selected blocks, creating a cleaner initial state that prevents hot carrier injection and read disturbance during subsequent programming and verification operations, thereby improving reliability.
2Quantity of substance
If multiple program loops are performed to program memory cells into multiple programming states, then the data storage capability is improved, but the programming time and verification complexity increase
Solution Approach 1:
The programming process uses periodic program loops with alternating programming and verification phases. Each program loop programs memory cells to a specific programming state and immediately verifies the result. This periodic structure enables efficient multi-level cell programming by systematically cycling through different voltage combinations to achieve multiple stable states while maintaining reasonable programming speeds.
Solution Approach 2:
Verification operations provide feedback on the programming state of memory cells. The verification results determine whether additional program loops are needed and adjust subsequent programming voltages. This feedback mechanism ensures accurate programming of multiple states while minimizing unnecessary programming cycles, optimizing the balance between storage capability and programming time.
3Reliability
If a soft erase operation is performed on unselected memory cell strings during verification intervals, then read disturbance is reduced, but the operation complexity increases
Solution Approach 1:
The soft erase operation is merged with the verification interval of normal programming operations. Instead of performing soft erase as a separate operation, it is integrated into the existing verification timing structure. The same verification circuitry and timing mechanisms are used to perform both verification and soft erase, reducing overall operation complexity while maintaining read accuracy improvements.
Solution Approach 2:
The verification operation serves multiple functions: it verifies the programming state of selected memory cells and simultaneously performs soft erase on unselected memory cell strings. This multi-functionality reduces the need for separate dedicated soft erase circuitry and operations, simplifying the overall device architecture while achieving both read disturbance reduction and verification goals.
Data Source
AI summary
A soft erase method of a memory device including applying a program voltage to a first memory cell in at least one of program loops when a plurality of program loops are performed to program the first memory cell into a Nth programming state, wherein the first memory cell is included in a selected memory cell string connected to a selected first bit line and is connected to a selected word line; and soft erasing a second memory cell by applying, in a first verification interval, a read voltage for verifying a programming state of the first memory cell to the selected word line and applying a first prepulse to a gate of a string select transistor of each of a plurality of unselected memory cell strings connected to the first bin line and a plurality of unselected memory cell strings connected to an unselected second bit line.