Soft Error Detection in Programmable Logic Devices
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Solution Overview
Problem
Programmable logic devices (PLDs) are prone to single event upset (SEU) failures due to their susceptibility to neutron-induced errors, which can cause soft or catastrophic failures, and existing mitigation techniques are not optimally effective for these devices.
Innovation Solution
Implementing a method and apparatus for soft-error upset detection and correction within integrated circuits, involving the installation of check stops in processor executable applications, collection of state information, and execution of error correction mechanisms to halt and correct errors, utilizing both software and hardware-based mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PLDs use configuration memory cells to control functionality, then adaptability and programmability are improved, but susceptibility to SEU failures increases
Solution Approach 1:
The patent implements preliminary actions by executing check stops at predetermined intervals to verify configuration memory integrity before errors occur. The system proactively collects state information and verifies configuration correctness at scheduled intervals, allowing detection and correction of SEUs before they cause catastrophic failures, thus resolving the contradiction between programmability and reliability.
Solution Approach 2:
The patent establishes feedback mechanisms where the system continuously monitors configuration memory integrity through check stops and state information collection. When errors are detected, the system receives feedback about the error condition and automatically executes correction routines, creating a closed-loop system that maintains reliability while preserving adaptability.
2Reliability
If check stops are executed at programmable time intervals, then error detection capability is improved, but system operation time is reduced
Solution Approach 1:
The patent applies periodic action by executing check stops at predetermined time intervals rather than continuously. This periodic verification approach maintains error detection capability while allowing the system to operate between check points, thus minimizing time loss compared to continuous monitoring. The system balances reliability and operational efficiency through scheduled verification cycles.
Solution Approach 2:
The patent implements partial action by performing check stops at specific intervals rather than continuous verification. This partial verification approach provides sufficient error detection capability for the application while reducing the total time consumed by monitoring operations, optimizing the balance between reliability improvement and time loss minimization.
3Reliability
If state information is collected at check stops, then error correction accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses copying by creating copies of state information at check stops. Instead of maintaining complex real-time monitoring of all system states, the system collects and stores snapshots of critical state information at predetermined intervals. This copying approach simplifies the monitoring mechanism while providing accurate error correction by comparing current state against previously copied state information.
Solution Approach 2:
The patent applies extraction by selectively collecting only the necessary state information at check stops rather than capturing all system state data. This selective extraction approach reduces the complexity of what needs to be monitored and stored, while still providing sufficient information for accurate error detection and correction, thus resolving the contradiction between correction accuracy and device complexity.
Data Source
AI summary
A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check stop facilitates a snap shot of the hardware and/or software state of the IC to be stored into hardware and/or software based memory. Should a soft error be detected, execution is halted and the executable state of the IC that conforms to a previous check-stop location may be re-established after the soft error(s) are optionally corrected. In alternate embodiments, hardware based mechanisms may be exclusively utilized to both detect and correct the soft errors.