Soft Error Immune Memory Cell With Segmented Feedback
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Solution Overview
Problem
Volatile memory elements in integrated circuits, such as those used in programmable logic devices, are susceptible to soft error upsets caused by cosmic rays and radioactive impurities, leading to data corruption and performance issues, particularly in remote telecommunications equipment installations.
Innovation Solution
The development of memory cells with interconnected inverter-like transistor pairs and distributed logic inputs, which provide redundancy and resistance to soft error upsets through the use of PMOS and NMOS transistors, address transistors, and capacitance to prevent rapid state changes, ensuring data retention even after radiation strikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If volatile memory elements are used in integrated circuits, then the circuit can be fabricated with standard technology and powered operation is maintained, but the memory elements become susceptible to soft error upsets from cosmic rays and radioactive impurities
Solution Approach 1:
The memory element is divided into multiple storage nodes (first and second storage nodes) with separate feedback paths. Each node is monitored by dedicated transistors (first and second p-channel transistors, third and fourth n-channel transistors) that independently detect and correct errors, segmenting the error correction function across multiple components rather than using a single vulnerable storage element
Solution Approach 2:
Different transistors are strategically positioned at specific storage nodes to provide localized error detection and correction. The first p-channel transistor is connected to the first storage node, while the second p-channel transistor is connected to the second storage node, creating local quality variations that enable targeted soft error immunity at each critical node
2Duration of action of stationary object
If nonvolatile memory elements are used, then data retention after power loss is achieved, but fabrication complexity increases and integration with programmable logic becomes difficult
Solution Approach 1:
The memory element uses standard CMOS transistors (p-channel and n-channel) that are universally available in programmable logic device fabrication processes. The same transistor types and interconnection methods used for logic circuits are employed for the memory function, allowing the memory element to be fabricated using existing technology without requiring specialized nonvolatile memory processes
3Reliability
If soft error immunity is improved through additional transistors and feedback paths, then reliability increases, but device complexity and area increase
Solution Approach 1:
The error detection and correction functions are merged into the existing feedback paths of the latch structure. The first and second p-channel transistors are integrated into the feedback path from the first storage node, while the third and fourth n-channel transistors are integrated into the feedback path from the second storage node, combining error correction with the fundamental latch operation rather than adding separate correction circuits
Data Source
AI summary
Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.