Soft Error Analysis and ECC Wrappers for Memory FIT Reduction
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Solution Overview
Problem
Current methods for estimating failure rates due to soft errors in electronic designs are inadequate, as they often underestimate failure rates in sequential and non-sequential elements, are prone to human errors, and are typically conducted late in the design cycle, causing delays and requiring additional manpower.
Innovation Solution
A method is provided to analyze failure rates by creating lists of storage elements, computing FIT rates, and inserting error-correction code wrappers and parity checks to reduce failure rates, using Register Transfer Language (RTL) descriptions and netlists to accurately report soft error rates and detect single-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes (SECDED) are added to memory to reduce failure rates, then reliability is improved, but device complexity and project schedule are worsened due to re-design requirements
Solution Approach 1:
The patent extracts the error correction functionality into separate wrapper modules that can be independently applied to specific memory blocks. Instead of redesigning the entire memory system with SECDED logic integrated throughout, the solution isolates error correction to only those memory blocks that require it, based on automated analysis of soft error rates and criticality.
Solution Approach 2:
The patent performs preliminary automated analysis of the design to identify which memory blocks require error correction and determines the optimal placement of SECDED logic before finalization. This preliminary action prevents later re-design by establishing error correction requirements early in the design process through automated soft error rate computation and criticality assessment.
2Reliability
If parity checks are added to flip-flop banks to detect soft errors, then reliability is improved, but device complexity and project schedule are worsened due to additional design changes and verification
Solution Approach 1:
The patent implements self-service through automated tools that perform soft error rate computation, criticality assessment, and wrapper insertion without requiring manual intervention. The system automatically generates the necessary parity check logic and integrates it into the design, eliminating the need for manual design changes and reducing verification burden.
Solution Approach 2:
The patent replaces manual mechanical processes (questionnaires, spreadsheets, manual analysis) with automated computational tools. The automated soft error rate computation and wrapper insertion tools substitute for manual engineering efforts, reducing both device complexity and verification requirements while improving reliability.
3Adaptability or versatility
If manual questionnaires are used to analyze failure rates, then flexibility is improved, but productivity and accuracy are worsened due to human errors and omissions
Solution Approach 1:
The patent replaces manual mechanical questionnaire processes with automated computational tools that compute soft error rates directly from design data. This substitution eliminates human errors and omissions while significantly improving productivity, as the automated tools can process entire designs systematically without manual intervention.
Solution Approach 2:
The patent introduces automated analysis tools as intermediaries between the design data and failure rate assessment. These tools act as mediators that systematically process design information, compute soft error rates, and generate results without human intervention, thereby improving both productivity and accuracy while maintaining flexibility through programmable analysis methods.
4Reliability
If comprehensive soft error analysis is performed early in the design cycle, then reliability is improved, but productivity is worsened due to additional time required for analysis
Solution Approach 1:
The patent replaces manual, time-consuming analysis methods with automated computational tools that can perform comprehensive soft error rate computation and criticality assessment rapidly. This automation enables early analysis in the design cycle without significantly impacting productivity, as the automated tools process design data much faster than manual methods.
Solution Approach 2:
The patent performs preliminary automated analysis early in the design cycle to identify critical blocks requiring error correction. This preliminary action improves reliability by establishing error correction requirements early, while the automated nature of the analysis minimizes the time required, thus not significantly worsening productivity.
Data Source
AI summary
Systems and methods for analyzing and reducing the failure rates due to soft errors in a design are provided. One such method involves analyzing the design by reading the design from a register-transfer-level language description or a netlist, manufacturing process soft error information, library information and timing constraints for the design to generate the failure in time (FIT) rate for the modules in the design. Another such method involves using the design and a list of memories that need error correction code inserted automatically and limiting the impact to the clock cycle, by analyzing the timing to the inputs and from the outputs of the memories and inserting an in-line or a late timing wrapper, which includes the ECC insert during writes, and ECC check and correct during reads, identifying the registers that need to be shadowed and used in the delayed ECC correct cycle, identifying the clock gating required for various elements in the design to get the correct logic at the conclusion of the re-play cycle of ECC correction in case of late timing ECC correction.