Soft Error-Mitigating Semiconductor Design System
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Solution Overview
Problem
Current semiconductor design methodologies face challenges in effectively mitigating Single Event Effects (SEEs) such as Single Event Upsets (SEUs) and Single Event Transients (SETs), which can compromise the reliability of electronic systems, especially in high-energy physics applications, due to the limitations of existing Triple Modular Redundancy (TMR) implementations in terms of area and power consumption, and the need for optimized circuit design specifications.
Innovation Solution
A soft error-mitigating semiconductor design system that automates the process of generating TMR configurations with triplicated cells, applying additional spacing constraints, and inserting clock delays or triplication during synthesis and physical design to optimize the distance between memory elements and prevent glitch propagation, thereby enhancing the resilience of digital designs to SEEs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Triple Modular Redundancy (TMR) is implemented to mitigate SEUs, then reliability is improved, but area and power consumption increase
Solution Approach 1:
The design system segments the TMR implementation into distinct phases: synthesis-phase triplication of sequential elements, placement-phase spatial separation constraints, and routing-phase clock delay insertion. This segmentation allows each aspect to be optimized independently, reducing the overall area overhead compared to monolithic TMR approaches.
Solution Approach 2:
The patent introduces spatial separation constraints in the placement dimension and clock timing adjustments in the time dimension, moving beyond simple logical triplication. By utilizing these additional design dimensions, the system achieves TMR functionality with reduced area overhead and improved power efficiency.
2Reliability
If Triple Modular Redundancy (TMR) is implemented to mitigate SEUs, then reliability is improved, but power consumption increases
Solution Approach 1:
The power consumption issue is addressed by segmenting the TMR approach into selective triplication of critical sequential elements rather than blanket triplication of all logic. The synthesis subsystem identifies and triplicates only those sequential elements that require protection, reducing overall power consumption while maintaining reliability for critical functions.
Solution Approach 2:
The system applies different levels of redundancy to different parts of the design based on their criticality. By using spacing constraints and clock delays locally at vulnerable sequential elements rather than globally across the entire design, power consumption is optimized while maintaining protection where most needed.
3Reliability
If spacing constraints are applied to separate memory elements, then SET mitigation is improved, but design complexity increases
Solution Approach 1:
The spacing constraints for SET mitigation are applied as preliminary directives during the synthesis phase, before placement and routing. This preliminary action allows the placement tool to automatically satisfy spacing requirements without requiring manual intervention or iterative adjustments, thereby reducing design complexity despite the additional constraints.
Solution Approach 2:
The design system uses automated tools that self-adjust the placement of sequential elements to satisfy spacing constraints. The placement tool automatically positions triplicated sequential elements at required distances from each other without manual configuration, and the routing tool automatically inserts appropriate clock delays, reducing the perceived complexity for the designer.
4Reliability
If clock delays are inserted to prevent glitch propagation, then SET mitigation is improved, but device complexity increases
Solution Approach 1:
Clock delay elements act as intermediaries between the clock signal and the triplicated sequential elements. These delay elements are automatically inserted and configured by the routing subsystem to create the necessary timing skew that prevents glitch propagation, thereby reducing the complexity of manually designing timing adjustment circuitry.
Solution Approach 2:
The system changes the timing parameters of clock signals delivered to different instances of triplicated sequential elements. By automatically adjusting clock phase and delay parameters during routing, the system achieves glitch mitigation without adding complex control logic or manual timing configuration.
Data Source
AI summary
A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.