Soft Error Rate Estimation for Logic Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current techniques for detecting and mitigating soft errors in integrated circuits are costly and often result in either inadequate or excessive reliability due to uncertainty in the actual soft error rate during system design, as they are selected without accurate prediction of the soft error rate, which depends on various environmental and system factors.
Innovation Solution
A method and system that estimate the rate of corruption of storage bits in logic circuits by inputting environmental descriptions, including altitude, latitude, longitude, and solar activity, to calculate the atomic particle flux density and determine the rate of corruption, using reference corruption rates and quantification of storage bits, allowing for accurate prediction and documentation of soft error rates and system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If detection and mitigation techniques for soft errors are implemented, then system reliability is improved, but system cost and complexity increase
Solution Approach 1:
The patent performs preliminary calculation of soft error rates during the system design phase by considering environmental factors (altitude, latitude, longitude, solar activity) and circuit characteristics (storage bit quantification). This allows designers to predict reliability requirements before implementation, enabling informed decisions about whether mitigation techniques are necessary and what level of protection is adequate, thereby avoiding unnecessary complexity.
2Reliability
If detection and mitigation techniques for soft errors are implemented, then system reliability is improved, but system cost increases
Solution Approach 1:
The patent enables preliminary reliability assessment during design by calculating soft error rates based on environmental conditions and circuit properties. This allows cost-effective decision-making by identifying systems that truly need mitigation techniques versus those that can operate without them, avoiding unnecessary expenditure on detection and mitigation hardware for low-risk applications.
Solution Approach 2:
The patent calculates soft error rates as a function of multiple parameters including altitude, latitude, longitude, solar activity level, and storage bit quantification. By varying these parameters, the system determines the actual risk level for each specific application, allowing proportional investment in mitigation techniques rather than universal implementation, thus optimizing cost-effectiveness.
3Reliability
If detection and mitigation techniques for soft errors are implemented, then system reliability is improved, but implementation difficulty and time increase
Solution Approach 1:
The patent performs soft error rate calculations during the design phase using environmental parameters and circuit characteristics, providing advance knowledge of reliability requirements. This preliminary assessment guides the selection and implementation of appropriate mitigation techniques, making the implementation process more systematic and less trial-and-error driven, thereby reducing implementation difficulty and time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate prediction of soft error rates during system design, ensuring adequate reliability without unnecessary costly mitigation techniques, thus optimizing system design by considering multiple factors and providing documented calculations for reliability and availability.
Implementation Method 1
When cosmic radiation strikes an integrated circuit, the high-energy atomic particles can create a string of hole and electron pairs in a substrate of the integrated circuit
Data Source
AI summary
Methods and systems estimate a rate of corruption of storage bits in a logic circuit. One or more processors execute instructions that cause the processors to perform the operations that follow. A description is input describing an environment of the logic circuit, and the description of the environment includes a position of the logic circuit. An atomic particle flux density at the logic circuit is estimated as a function of the description of the environment. A specification is input that specifies the storage bits in the logic circuit. The rate of corruption of the storage bits is determined as a function of the atomic particle flux density and a quantification of the storage bits in the logic circuit.