Soft Error Recovery Flip-Flop Using Gated Feedback Storage
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Solution Overview
Problem
Modern microprocessors are susceptible to radiation-induced soft errors due to decreasing node capacitance and power supply voltage, leading to increased susceptibility to logic failures, and existing methods to combat these errors, such as using larger capacitance nodes or redundant latches, result in increased area and propagation delay.
Innovation Solution
A flip-flop circuit design that incorporates a soft error recovery (SER) circuitry, allowing data and feedback storage values to be stored on separate nodes using both ungated and gated clock signals, enabling recovery without a clock signal transition, thereby reducing the susceptibility to soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger capacitance nodes or redundant latches are used to combat soft errors, then soft error tolerance is improved, but area and propagation delay increase
Solution Approach 1:
The invention segments the storage function into two separate nodes: a first node for storing the primary data value and a second node for storing feedback storage values. This segmentation allows independent optimization of each node's capacitance and enables selective recovery of the feedback node without affecting the primary data storage, thereby improving soft error tolerance without proportionally increasing area.
Solution Approach 2:
The invention introduces an intermediary recovery mechanism that uses the separation of data and feedback storage to enable error correction. The feedback storage value on the second node serves as an intermediary that can be used to recover and correct errors in the primary data on the first node, providing soft error tolerance without requiring full redundancy of the entire flip-flop structure.
2Reliability
If larger capacitance nodes or redundant latches are used to combat soft errors, then soft error tolerance is improved, but propagation delay increases
Solution Approach 1:
By segmenting the storage into separate nodes for data and feedback values, the invention allows the feedback node to be optimized for quick recovery operations while the primary data node maintains standard timing characteristics. This segmentation enables faster error correction without delaying the main data path.
Solution Approach 2:
The feedback storage value is preliminarily maintained on the second node in readiness for potential error recovery. This preliminary action allows the recovery process to occur quickly when needed, without requiring time-consuming error detection and correction sequences that would increase propagation delay through the main data path.
3Loss of energy
If power supply voltage is decreased to reduce power consumption and electrostatic fields, then power consumption is reduced, but transistor leakage current increases
Solution Approach 1:
The invention employs a feedback storage node that can be rapidly refreshed and recovered without requiring high voltage levels. This allows the use of lower power supply voltages while maintaining data integrity through the recovery mechanism, effectively tolerating the increased leakage current that comes with reduced voltage by using the separate feedback node for periodic restoration of valid data states.
Data Source
AI summary
A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal.