Soft FEC Parity Checks for High-Speed Worst-Symbol Correction
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Solution Overview
Problem
Existing data communication systems face challenges in efficiently handling high-speed data transfer and error correction, particularly in systems like 802.3bs, where they struggle to manage the large amounts of bandwidth required for multimedia data and maintain accuracy.
Innovation Solution
The implementation of a data transmission device with a Reed-Solomon encoder and decoder that generates and uses parity symbols within FEC blocks, allowing for error correction by identifying and modifying the worst symbols based on log-likelihood ratios and parity checks, integrated into existing communication systems with minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional FEC schemes are used in high-speed data transfer systems, then data transmission speed can be maintained, but data transmission accuracy and error correction capability deteriorate
Solution Approach 1:
The data stream is divided into segments with odd and even parity bits assigned to different segments. The encoder separates odd and even symbols into different streams, applies different parity checks to each segment, and transmits them through different communication lanes. This segmentation allows independent error correction for each segment while maintaining high transmission speed.
Solution Approach 2:
The patent introduces a new dimension of error correction by adding parity symbols in addition to the traditional Reed-Solomon coding. The parity symbols provide an additional layer of error detection and correction capability, enabling the system to achieve both high speed and high accuracy simultaneously.
2Reliability
If complex error correction algorithms are implemented, then data transmission accuracy improves, but computational complexity and processing time increase
Solution Approach 1:
The decoder complexity is reduced by segmenting the error correction process into separate odd and even parity check operations. Each segment is processed independently using simple parity comparison, avoiding the need for complex unified error correction algorithms while maintaining high reliability.
Solution Approach 2:
Instead of implementing full complex error correction for all symbols, the patent applies partial action by only performing error correction when parity mismatches are detected. The decoder first checks parity conditions, and only then performs the necessary correction operations, reducing overall computational complexity.
3Reliability
If more redundancy bits are added for error correction, then error correction capability improves, but data transmission rate decreases
Solution Approach 1:
The patent applies local quality by adding parity bits only to specific segments (odd and even segments separately) rather than uniformly to all data. This targeted approach provides error correction capability where needed while minimizing the overall overhead and maintaining high transmission rates.
Solution Approach 2:
The system uses partial action by adding redundancy only when necessary - specifically when parity mismatches are detected. The parity symbols are generated and applied selectively to correct errors, rather than continuously adding maximum redundancy, thus maintaining high data transmission rates while providing sufficient error correction capability.
Data Source
AI summary
The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.