Soft FEC Parity Check for High-Speed Data Transmission
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Solution Overview
Problem
Existing data communication systems face challenges in handling high-speed data transfer and error correction, particularly in managing large volumes of multimedia data, where current protocols like 802.3 bs and 802.3 cd require improvements to maintain accuracy and efficiency.
Innovation Solution
The implementation of a Forward Error Correction (FEC) system that processes interleaved data streams, generates parity symbols, and embeds them into FEC blocks, allowing for error correction by selecting and correcting the worst symbol based on parity checks, which can be easily integrated into existing systems like PAM4 based high-speed data communication systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FEC schemes are used in high-speed data communication, then data transfer speed can be maintained, but error correction capability and power efficiency deteriorate
Solution Approach 1:
The patent segments the data stream into interleaved blocks and processes them in parallel using multiple FEC encoders. Each encoder handles a subset of data blocks independently, enabling distributed error correction processing that reduces computational complexity and power consumption while maintaining comprehensive error coverage across the entire data stream.
Solution Approach 2:
The patent applies partial FEC encoding to specific segments of data rather than encoding the entire stream uniformly. By identifying and protecting only the most critical or error-prone data portions with FEC, the system achieves adequate error correction capability with reduced processing overhead and lower power consumption compared to full-stream encoding.
2Reliability
If FEC encoding is applied to correct errors, then data transmission reliability improves, but transmission overhead increases
Solution Approach 1:
The patent applies different FEC encoding strategies to different segments of the data stream based on their specific requirements. Critical data segments receive enhanced FEC protection while less critical segments use lighter encoding, optimizing the balance between error correction coverage and overhead minimization across the entire transmission.
Solution Approach 2:
The patent performs preliminary data sorting and segmentation before FEC encoding, organizing data blocks in advance to enable more efficient parallel processing. This preliminary organization allows the FEC encoders to operate more efficiently with reduced computational overhead, thereby minimizing the additional transmission resources required for error correction.
3Speed
If existing communication protocols like 802.3 bs are used, then high-speed data transfer is achieved, but error correction performance deteriorates
Solution Approach 1:
The patent merges multiple FEC encoding functions into a unified parallel processing architecture that operates alongside existing high-speed communication protocols. By integrating FEC encoding/decoding operations with the data transfer pipeline rather than separating them as distinct stages, the system maintains high data transfer speeds while achieving robust error correction performance.
Solution Approach 2:
The patent implements dynamic FEC encoding/decoding that adapts to real-time transmission conditions. The system can adjust encoding parameters and error correction intensity based on observed channel quality and error rates, allowing optimal error correction performance to be achieved without consistently consuming the overhead and processing resources required for aggressive fixed-rate correction schemes.
Data Source
AI summary
A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.