Soft FEC Parity Check for Worst-Symbol Error Correction
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Solution Overview
Problem
Existing data communication systems face challenges in efficiently handling high-speed data transfer and error correction, particularly in systems like 802.3bs and 802.3cd, where high bandwidth demands and multimedia data processing require improved techniques to maintain accuracy and reduce bit-error rates.
Innovation Solution
The implementation of a Forward Error Correction (FEC) system that generates parity symbols embedded into FEC blocks, allowing for error correction by selecting and correcting the worst symbol based on parity checks, which can be easily integrated into existing systems like PAM4-based communication systems, providing low-power and low-overhead solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional FEC systems are used for high-speed data transfer, then data transmission capability is improved, but bit-error rates increase and require more complex error correction mechanisms
Solution Approach 1:
The data stream is divided into even and odd blocks that are processed separately through different delay lines and multiplexed. This segmentation allows the system to handle high-speed data transfer while maintaining error correction capability by treating different portions of data independently, thus resolving the contradiction between speed and reliability
Solution Approach 2:
Parity bits are pre-calculated and embedded into FEC blocks before transmission. This preliminary action enables the receiver to perform error detection and correction without requiring complex real-time processing, allowing high-speed transmission while maintaining low bit-error rates
2Reliability
If advanced error correction techniques are implemented, then bit-error rates are reduced, but system complexity and power consumption increase
Solution Approach 1:
The system performs parity checks on selected symbols rather than all symbols, and corrects only the worst symbol in each block. This partial action approach achieves effective error correction with reduced computational complexity and lower power consumption compared to comprehensive error correction methods
Solution Approach 2:
The system uses embedded parity bits within the data stream itself to perform self-diagnosis and self-correction. The even and odd parity bits enable the receiver to identify and correct errors without external intervention, reducing system complexity while maintaining high reliability
3Reliability
If comprehensive error correction is performed on all symbols, then reliability is improved, but processing time and power consumption increase
Solution Approach 1:
The system applies error correction resources selectively to the worst symbol in each block rather than uniformly to all symbols. This local quality approach concentrates correction efforts where they are most needed, achieving high reliability with minimal power consumption by avoiding unnecessary processing of already-correct symbols
Data Source
AI summary
The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.