Top-Down Physical Design of Soft FPGA Fabrics for Global Timing
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Solution Overview
Problem
Existing synthesizable FPGA fabrics face challenges in ensuring global timing views across multiple tiles, leading to combinational loops and long false paths, which complicates integration with ASIC blocks and requires manual buffering and floorplanning, making them incompatible with typical SoC design schedules.
Innovation Solution
A top-down design methodology is employed to provide a global timing view of the FPGA fabric to EDA tools, restructuring switch-box multiplexers to enable static timing analysis exceptions, eliminating the need for manual buffering and floorplanning, and allowing for a push-button ASIC design flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bottom-up methodology is used to synthesize individual tiles in isolation, then ease of manufacture is improved, but device complexity increases due to lack of global timing view across multiple tiles
Solution Approach 1:
The patent divides the FPGA fabric into modular tiles that can be synthesized independently using bottom-up methodology, yet maintains global timing control through a hierarchical approach where each tile is a self-contained unit with standardized interfaces
Solution Approach 2:
The patent introduces an intermediary layer of abstraction that connects individual tiles to the global timing system, allowing local tile synthesis while maintaining fabric-level performance through coordinated timing constraints and interface standardization
2Manufacturing precision
If floorplanning and manual buffer insertion are used to address timing issues, then manufacturing precision is improved, but device complexity increases and ease of operation deteriorates
Solution Approach 1:
The patent enables the synthesis tool to automatically handle timing constraints and buffer insertion through standardized interfaces, eliminating the need for manual floorplanning and buffer insertion while maintaining precise timing control through self-service mechanisms
3Ease of manufacture
If soft eFPGA fabrics are implemented using RTL design abstraction, then ease of manufacture is improved, but device complexity increases due to difficulty in providing global timing view
Solution Approach 1:
The patent introduces an intermediary timing constraint system that bridges RTL design abstraction with global timing requirements, allowing soft eFPGA fabrics to maintain both RTL portability and fabric-level timing control through standardized timing interfaces
Data Source
AI summary
Disclosed herein is a method for performing top-down design for optimizing synthesizable FPGA fabrics which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric to the electronic design automation (EDA) tools. This is accomplished by providing the EDA tools with a global timing view spanning multiple tiles. The method restructures the switch-box muliplexers in a unique way to enable the use of powerful static timing analysis (STA) exceptions supported by modern EDA tools to work around the problem of combinational loops and long false paths created by the interconnect mesh in the FPGA fabric.