Soft and Hard Memory Block Closures for Write Amplification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory sub-systems fail to adequately address the temporal voltage shift caused by slow charge loss in memory cells, leading to increased bit error rates due to inefficient strategies.
Innovation Solution
Implementing a memory sub-system that tracks temporal voltage shift for grouped block families, applying appropriate voltage offsets based on block affiliation, and performing soft and hard closures to manage the shift, thereby improving bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory sub-systems use traditional closure strategies for block families, then device complexity is reduced, but bit error rates increase due to inadequate handling of temporal voltage shift
Solution Approach 1:
The patent segments block families into different categories (open, soft-closed, hard-closed) based on their voltage distribution characteristics and time since programming. This segmentation allows the system to apply different management strategies to different segments, improving bit error rates by针对性地 handling temporal voltage shift while maintaining manageable complexity through structured categorization.
Solution Approach 2:
The patent performs preliminary classification of block families into soft-closed and hard-closed categories based on predetermined time thresholds and voltage distribution characteristics. This preliminary action enables the system to proactively apply appropriate voltage offsets and closure strategies before significant voltage drift occurs, thereby reducing bit error rates while maintaining systematic control.
2Measurement precision
If memory sub-systems implement tracking and calibration operations for all blocks, then measurement precision of voltage shift is improved, but processing and storage resources are consumed
Solution Approach 1:
The patent applies local quality by performing detailed voltage shift tracking and calibration operations only on block families that require it (based on their open/closed status and time since programming), rather than uniformly across all blocks. This selective approach maintains high measurement precision for critical blocks while conserving processing and storage resources by reducing unnecessary operations on less critical blocks.
Solution Approach 2:
The patent implements partial action by performing calibration operations on a subset of block families rather than all blocks. The system applies calibration selectively to soft-closed and hard-closed block families based on their specific needs, achieving sufficient voltage shift measurement precision without the excessive resource consumption that would result from universal calibration of all memory blocks.
3Manufacturing precision
If memory sub-systems perform frequent calibration operations, then manufacturing precision of voltage distribution is improved, but productivity decreases due to increased operation time
Solution Approach 1:
The patent implements periodic calibration operations based on time thresholds and block family status changes rather than continuous or frequent calibration. The system performs calibration at predetermined intervals and when block families transition between open, soft-closed, and hard-closed states, maintaining voltage distribution accuracy while minimizing interruptions to programming operations and preserving productivity.
Solution Approach 2:
The patent applies dynamic calibration scheduling that adapts to the actual state of block families. The system increases calibration frequency for recently programmed blocks that exhibit greater voltage drift, while reducing calibration frequency for older, stable blocks. This dynamic approach maintains manufacturing precision where needed while optimizing productivity by avoiding unnecessary calibration operations.
Data Source
AI summary
A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device initializes a block family associated with the memory device and a timer associated with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family and a hard closure of the block family in response to a first of the timer reaching a hard closure value or the block family satisfying a hard closure criteria. The processing device detects a first write amplification of a previously closed block family that employed the hard closure value and increases the hard closure value by an amount of time calculated to reduce a second write amplification, of the block family, to below a threshold write amplification.