Soft Mapper and Demapper LLR Generation for Block Codes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current coding techniques lack efficient methods for generating soft information using other soft information as input, particularly in hardware implementations like FPGAs or ASICs, which are capable of performing complex calculations but struggle with generating log-likelihood ratios (LLRs) for block codes effectively.
Innovation Solution
The development of soft input, soft output mappers and demappers that generate LLRs for block codes by utilizing existing LLRs, where the number of LLRs output is greater than the number of LLRs input, using techniques such as iterative max* functions and maximum functions to calculate LLR values, enabling hardware implementation in FPGAs or ASICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hard information output is used, then device complexity is reduced, but soft information generation capability is lost
Solution Approach 1:
The patent transforms the decoder output from hard decisions (binary 0/1) to soft information (log-likelihood ratios) by changing the parameter representation. The LLR calculation uses the formula LLR = ln(P(bit=0)/P(bit=1)), converting probability ratios into manageable logarithmic values that preserve uncertainty information while being suitable for hardware implementation.
Solution Approach 2:
The patent introduces an intermediary processing stage between the decoder and final output that generates soft information. This intermediary layer computes LLRs based on decoder metrics without requiring full soft-input soft-output decoding, thus adding minimal complexity while recovering soft information that would otherwise be lost.
2Reliability
If soft information processing is implemented, then error correction capability is improved, but hardware implementation difficulty increases
Solution Approach 1:
The patent employs simplified LLR generation methods that use approximate calculations rather than exact probabilistic computations. By using max* functions and lookup tables instead of full Bayesian inference, the implementation achieves acceptable error correction performance with significantly reduced hardware resources, effectively using 'cheap' approximate computations to achieve reliable soft information generation.
Solution Approach 2:
The patent transforms complex probabilistic calculations into simpler logarithmic domain operations. By working with LLRs instead of raw probabilities, the system enables hardware-friendly computations using addition and multiplication in the log domain, avoiding expensive division and exponentiation operations while maintaining error correction effectiveness.
3Measurement precision
If LLR generation for block codes is implemented, then soft information accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent divides the LLR generation process into separate independent calculations for each code bit. Instead of computing a single complex probability for the entire codeword, the system calculates individual LLRs for each bit position separately, allowing parallel implementation and reducing overall computational complexity while maintaining accuracy.
Solution Approach 2:
The patent uses lookup tables that store pre-computed LLR values based on decoder metrics. By copying and storing these pre-calculated values, the system avoids repeating complex computational operations during actual decoding, achieving both high accuracy and low real-time computational complexity through preprocessing.
Data Source
AI summary
A codebook which includes a plurality of messages and a plurality of codewords, a specified codeword bit value, and a specified message bit value are obtained. The LLR for bit ci in a codeword is generated, including by: identifying, from the codebook, those codewords where bit ci has the specified codeword bit value; for a message which corresponds to one of the codewords where bit ci has the specified codeword bit value, identifying those bits which have the specified message bit value; and summing one or more LLR values which correspond to those bits, in the message which corresponds to one of the codewords where bit ci has the specified codeword bit value, which have the specified message bit value.