Soft NoC Overlay for Partial Reconfiguration Continuity
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Solution Overview
Problem
Existing soft network-on-chip (NOC) technologies for integrated circuits perform inconsistently, operate at low speeds, struggle with routing wide buses across long spans, and fail to leverage fine granularity of partial reconfiguration regions, leading to difficulties in controlling data distribution and affecting NOC operation during design changes.
Innovation Solution
A soft NOC is designed as a static overlay that interacts with partial reconfiguration regions, allowing it to remain operational during partial reconfiguration, using specialized registers and routing multiplexers to construct high-speed point-to-point networks within these regions, enabling uninterrupted data transport and efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If soft NOC is implemented using existing soft logic programming methods, then the integrated circuit can be programmed flexibly, but the NOC performs inconsistently and operates at relatively low speeds
Solution Approach 1:
The NOC is segmented into specialized functional components including routing multiplexers, specialized registers, and configurable logic elements. Each segment is optimized for specific functions (routing, data storage, logic operations) rather than using general-purpose soft logic throughout, enabling higher speeds while maintaining programming flexibility through configurable interconnections between segments
Solution Approach 2:
Different regions of the integrated circuit are assigned different qualities and functions: static regions provide stable, high-speed routing infrastructure, while partial reconfiguration regions provide flexibility. The routing multiplexers and specialized registers are strategically placed in static regions to ensure consistent high-speed operation, while allowing flexible configuration in reconfigurable regions
2Length of moving object
If soft NOC routes wide buses across long spans of the integrated circuit, then communication between distant portions is enabled, but routing performance degrades and becomes inconsistent
Solution Approach 1:
The routing architecture transitions from two-dimensional plane routing to three-dimensional routing by utilizing multiple routing layers and vertical interconnects. Wide buses are routed across long spans by distributing them across multiple layers and using routing multiplexers at strategic points, maintaining signal integrity and consistent timing despite long distances
Solution Approach 2:
Routing multiplexers serve as intermediary elements between source and destination, particularly for wide buses spanning long distances. These multiplexers break down wide buses into smaller segments, route them through intermediate points with controlled timing, and reassemble them at the destination, ensuring consistent and reliable routing across long spans
3Stability of the object's composition
If the soft NOC is fused with static configuration, then design stability is improved, but design changes affect NOC operation
Solution Approach 1:
The NOC architecture implements dynamic configurability by separating static infrastructure (routing multiplexers, specialized registers, interconnect fabric) from dynamic user logic (partial reconfiguration regions). The static portions maintain stable, high-speed routing operations, while the dynamic portions can be reconfigured without affecting NOC functionality, allowing design changes while preserving operational stability
4Adaptability or versatility
If partial reconfiguration regions are used to enable design flexibility, then adaptability is improved, but existing soft NOC fails to leverage the fine granularity of these regions
Solution Approach 1:
The specialized registers and routing multiplexers are designed as universal components that serve multiple functions: they provide high-speed data storage and routing for NOC operations, while also being seamlessly integrated with partial reconfiguration regions. This multi-functionality allows the same infrastructure to support both stable NOC operations and flexible design reconfiguration, maximizing resource utilization
Solution Approach 2:
The routing multiplexers and specialized registers automatically manage data flow between static and partial reconfiguration regions without requiring external control logic. They self-adapt to the configuration state of adjacent reconfiguration regions, seamlessly routing data through the finest granularity boundaries and maximizing the utilization of partial reconfiguration capabilities
Data Source
AI summary
An integrated circuit device includes a programmable logic fabric that has programmable logic circuitry and a partial reconfiguration region. The integrated circuit device also includes a network-on-chip formed in soft logic of the integrated circuit device. Additionally, the network-on-chip is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region.